From 9241c78667ab96d8994f1ccc92799674ba9c59a8 Mon Sep 17 00:00:00 2001 From: Alex Richardson Date: Mon, 6 Jan 2025 16:00:33 -0800 Subject: [PATCH] riscv: Add missing parens around macro argument This triggered a out of range count overflow warning when building for RV32 (calling the macro with `ticks >> 32`) since the truncation happened before the shift. --- arch/riscv/include/arch/riscv.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/arch/riscv.h b/arch/riscv/include/arch/riscv.h index e1e1f0c2..835dda1a 100644 --- a/arch/riscv/include/arch/riscv.h +++ b/arch/riscv/include/arch/riscv.h @@ -180,7 +180,7 @@ __BEGIN_CDECLS #define riscv_csr_write(csr, val) \ ({ \ - ulong __val = (ulong)val; \ + ulong __val = (ulong)(val); \ __asm__ volatile( \ "csrw " __ASM_STR(csr) ", %0" \ :: "rK" (__val) \