riscv: Add missing parens around macro argument

This triggered a out of range count overflow warning when
building for RV32 (calling the macro with `ticks >> 32`)
since the truncation happened before the shift.

arch/riscv/include/arch/riscv.h

@@ -180,7 +180,7 @@ __BEGIN_CDECLS
 
 #define riscv_csr_write(csr, val) \
 ({ \
-    ulong __val = (ulong)val; \
+    ulong __val = (ulong)(val); \
     __asm__ volatile( \
         "csrw   " __ASM_STR(csr) ", %0" \
         :: "rK" (__val) \