[platform][sifive-e] get the hifive1 hardware working again

Had rotted a bit. Had to reimplement a few tweaks.
Also generally #if out a lot of the SMP code when unused on riscv.

arch/riscv/arch.c

@@ -94,11 +94,10 @@ void riscv_secondary_entry(void) {
 #endif
 
 void arch_idle(void) {
-    // disabled for now, QEMU seems to have some trouble emulating wfi properly
-    // also have trouble breaking into sifive-e board with openocd when wfi
-    // NOTE: reenabling for now, will need to re-test on sifive board to see if this
-    // problem went away.
+    // let the platform/target disable wfi
+#if !RISCV_DISABLE_WFI
     __asm__ volatile("wfi");
+#endif
 }
 
 void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3) {

arch/riscv/exceptions.c

@@ -46,9 +46,11 @@ void riscv_exception_handler(ulong cause, ulong epc, struct riscv_short_iframe *
 
     enum handler_return ret = INT_NO_RESCHEDULE;
     switch (cause) {
+#if WITH_SMP
         case int_bit | RISCV_EXCEPTION_XSWI: // machine software interrupt
             ret = riscv_software_exception();
             break;
+#endif
         case int_bit | RISCV_EXCEPTION_XTIM: // machine timer interrupt
             ret = riscv_timer_exception();
             break;

arch/riscv/include/arch/arch_ops.h

@@ -52,10 +52,17 @@ static inline void set_current_thread(struct thread *t) {
 }
 
 static inline uint32_t arch_cycle_count(void) {
+#if RISCV_M_MODE
+    // use M version of the cycle if we're in machine mode. Some
+    // cpus dont have a U mode alias for this.
+    return riscv_csr_read(RISCV_CSR_MCYCLE);
+#else
     return riscv_csr_read(RISCV_CSR_CYCLE);
+#endif
 }
 
 static inline uint arch_curr_cpu_num(void) {
+#if WITH_SMP
     const uint hart = riscv_current_hart();
     for (size_t i = 0; i < SMP_MAX_CPUS; i++) {
         if (hart_cpu_map[i] == (int)hart)
@@ -68,5 +75,8 @@ static inline uint arch_curr_cpu_num(void) {
         }
     }
     return -1;
+#else
+    return 0;
+#endif
 }
 

arch/riscv/include/arch/riscv.h

@@ -44,6 +44,7 @@
 #define RISCV_CSR_XIP       (0x044 | RISCV_CSR_XMODE_BITS)
 
 #if RISCV_M_MODE // Machine-mode only CSRs
+#define RISCV_CSR_MCYCLE    (0xb00)
 #define RISCV_CSR_MVENDORID (0xf11)
 #define RISCV_CSR_MARCHID   (0xf12)
 #define RISCV_CSR_MIMPID    (0xf13)
@@ -63,7 +64,6 @@
 #define RISCV_CSR_XIP_EIP       (1u << (RISCV_XMODE_OFFSET + 8))
 
 #define RISCV_EXCEPTION_XSWI        (RISCV_XMODE_OFFSET)
-
 #define RISCV_EXCEPTION_XTIM        (4 + RISCV_XMODE_OFFSET)
 #define RISCV_EXCEPTION_XEXT        (8 + RISCV_XMODE_OFFSET)
 

arch/riscv/mp.c

@@ -14,6 +14,8 @@
 #include <arch/ops.h>
 #include <arch/mp.h>
 
+#if WITH_SMP
+
 #define LOCAL_TRACE 0
 
 int hart_cpu_map[SMP_MAX_CPUS] = { [0 ... SMP_MAX_CPUS-1] = -1 };
@@ -33,6 +35,7 @@ status_t arch_mp_send_ipi(mp_cpu_mask_t target, mp_ipi_t ipi) {
         if (m & 1) {
             hart_mask |= (1 << h);
         }
+        // TODO: set the ipi_data based on the incoming ipi
     }
 
     asm volatile("	fence iorw,iorw");
@@ -73,3 +76,5 @@ void arch_mp_init_percpu(void) {
     dprintf(INFO, "\nRISCV: Booting hart%d (cpu%d)\n", riscv_current_hart(), arch_curr_cpu_num());
     riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_SIE);
 }
+
+#endif

platform/sifive/rules.mk

@@ -21,6 +21,10 @@ ifeq ($(VARIANT),sifive_e)
 ARCH_RISCV_TWOSEGMENT := 1
 # sets a few options in the riscv arch
 ARCH_RISCV_EMBEDDED := 1
+
+# disable WFI during idle. Have trouble breaking into a WFIed board
+# with openocd.
+GLOBAL_DEFINES += RISCV_DISABLE_WFI=1
 endif
 
 # sifive_e or _u?

target/sifive-e/rules.mk

@@ -4,6 +4,7 @@ MODULE := $(LOCAL_DIR)
 
 PLATFORM := sifive
 VARIANT := sifive_e
+WITH_LINKER_GC ?= 1
 
 MEMSIZE ?= 0x4000     # 16KB
 GLOBAL_DEFINES += TARGET_HAS_DEBUG_LED=1

target/sifive-e/target.c

@@ -26,6 +26,8 @@ void target_early_init(void) {
     // program the pll bypass, we should be running at 16Mhz now
     prci_base[2] = 0x00070df1;
 
+    // lfclock is a 32768Hz crystal, strapped externally
+
     // io function enable for pin 16/17, no IOF for all others
     gpio_base[14] = (3<<16);