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[arch][arm/arm64] Support systems with mutiple clusters

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Set SMP_CPU_CLUSTER_SHIFT to the number of bits needed within
each cluster.
All clusters except the last one, need to have the name number
of cpus to avoid gaps.

Also, add a SMP_CPU_ID_BITS variable and limit this to 8 bits
on the bcm2835 platform instead of ignoring cluster ids by default
on arm.

Change-Id: I1d0be1d9c99d5b85368ce71623e6e7d14fefd604
This commit is contained in:
Arve Hjønnevåg
2015-04-17 21:09:02 -07:00
parent 8985379e2f
commit 8f0d310616
7 changed files with 30 additions and 13 deletions
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16
arch/arm/arm/start.S
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@@ -68,14 +68,8 @@ arm_reset:
/* figure out our cpu number */
mrc p15, 0, r12, c0, c0, 5 /* read MPIDR */
#if 0
// XXX handle machines with weird cluster numbers
/* mask off the bottom 12 bits to test cluster number:cpu number */
ubfx r12, r12, #0, #12
#else
/* mask off the bottom 8 bits to test cpu number */
ubfx r12, r12, #0, #8
#endif
/* mask off the bottom bits to test cluster number:cpu number */
ubfx r12, r12, #0, #SMP_CPU_ID_BITS
/* if we're not cpu 0:0, fall into a trap and wait */
teq r12, #0
@@ -362,6 +356,12 @@ FUNCTION(arm_secondary_setup)
cmp r12, #0
bne 1b
and r1, r0, #0xff
cmp r1, #(1 << SMP_CPU_CLUSTER_SHIFT)
bge unsupported_cpu_trap
bic r0, r0, #0xff
orr r0, r1, r0, LSR #(8 - SMP_CPU_CLUSTER_SHIFT)
cmp r0, #SMP_MAX_CPUS
bge unsupported_cpu_trap

3
arch/arm/include/arch/arch_ops.h
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@@ -235,7 +235,8 @@ static inline uint32_t arch_cycle_count(void)
#if WITH_SMP && ARM_ISA_ARMV7
static inline uint arch_curr_cpu_num(void)
{
return arm_read_mpidr() & 0x3;
uint32_t mpidr = arm_read_mpidr();
return ((mpidr & ((1U << SMP_CPU_ID_BITS) - 1)) >> 8 << SMP_CPU_CLUSTER_SHIFT) | (mpidr & 0xff);
}
#else
static inline uint arch_curr_cpu_num(void)

6
arch/arm/rules.mk
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@@ -198,10 +198,14 @@ GLOBAL_DEFINES += \
# if its requested we build with SMP, arm generically supports 4 cpus
ifeq ($(WITH_SMP),1)
SMP_MAX_CPUS ?= 4
SMP_CPU_CLUSTER_SHIFT ?= 8
SMP_CPU_ID_BITS ?= 24
GLOBAL_DEFINES += \
WITH_SMP=1 \
SMP_MAX_CPUS=$(SMP_MAX_CPUS)
SMP_MAX_CPUS=$(SMP_MAX_CPUS) \
SMP_CPU_CLUSTER_SHIFT=$(SMP_CPU_CLUSTER_SHIFT) \
SMP_CPU_ID_BITS=$(SMP_CPU_ID_BITS)
MODULE_SRCS += \
$(LOCAL_DIR)/arm/mp.c

3
arch/arm64/include/arch/arch_ops.h
View File

@@ -246,7 +246,8 @@ static inline void set_current_thread(struct thread *t)
static inline uint arch_curr_cpu_num(void)
{
return ARM64_READ_SYSREG(mpidr_el1) & 0x3;
uint64_t mpidr = ARM64_READ_SYSREG(mpidr_el1);
return ((mpidr & ((1U << SMP_CPU_ID_BITS) - 1)) >> 8 << SMP_CPU_CLUSTER_SHIFT) | (mpidr & 0xff);
}
#endif // ASSEMBLY

6
arch/arm64/rules.mk
View File

@@ -32,10 +32,14 @@ GLOBAL_DEFINES += \
# if its requested we build with SMP, arm generically supports 4 cpus
ifeq ($(WITH_SMP),1)
SMP_MAX_CPUS ?= 4
SMP_CPU_CLUSTER_SHIFT ?= 8
SMP_CPU_ID_BITS ?= 24 # Ignore aff3 bits for now since they are not next to aff2
GLOBAL_DEFINES += \
WITH_SMP=1 \
SMP_MAX_CPUS=$(SMP_MAX_CPUS)
SMP_MAX_CPUS=$(SMP_MAX_CPUS) \
SMP_CPU_CLUSTER_SHIFT=$(SMP_CPU_CLUSTER_SHIFT) \
SMP_CPU_ID_BITS=$(SMP_CPU_ID_BITS)
MODULE_SRCS += \
$(LOCAL_DIR)/mp.c

8
arch/arm64/start.S
View File

@@ -49,7 +49,7 @@ FUNCTION(_start)
#if WITH_SMP
mrs cpuid, mpidr_el1
bic cpuid, cpuid, #0xff000000
ubfx cpuid, cpuid, #0, #SMP_CPU_ID_BITS
cbnz cpuid, .Lmmu_enable_secondary
#endif
@@ -295,6 +295,12 @@ FUNCTION(_start)
#if WITH_SMP
.Lsecondary_boot:
and tmp, cpuid, #0xff
cmp tmp, #(1 << SMP_CPU_CLUSTER_SHIFT)
bge .Lunsupported_cpu_trap
bic cpuid, cpuid, #0xff
orr cpuid, tmp, cpuid, LSR #(8 - SMP_CPU_CLUSTER_SHIFT)
cmp cpuid, #SMP_MAX_CPUS
bge .Lunsupported_cpu_trap

1
platform/bcm2835/rules.mk
View File

@@ -5,6 +5,7 @@ MODULE := $(LOCAL_DIR)
ARCH := arm
ARM_CPU := cortex-a7
WITH_SMP := 1
SMP_CPU_ID_BITS := 8
MODULE_DEPS := \
dev/timer/arm_generic \