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[arch][riscv] Initial port to a riscv32 sifive target

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Currently targets qemu's sifive_e machine, which is a split flash/ram
machine, much like the Sifive HiFive1. Untested as of yet on a real
HiFive1.

Basic support including interrupts and architectural timers in place.
This commit is contained in:
Travis Geiselbrecht
2018-10-14 17:12:01 -07:00
parent fdb41e1d8b
commit 8cf28bbdcf
29 changed files with 1467 additions and 5 deletions
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4
scripts/do-qemuriscv32 Executable file
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#!/bin/sh
make qemu-riscv32-test -j4 &&
qemu-system-riscv32 -machine sifive_e -kernel build-qemu-riscv32-test/lk.elf -nographic $@