[arch][riscv] Initial port to a riscv32 sifive target

Currently targets qemu's sifive_e machine, which is a split flash/ram
machine, much like the Sifive HiFive1. Untested as of yet on a real
HiFive1.

Basic support including interrupts and architectural timers in place.

lib/libc/string/arch/riscv/rules.mk

@@ -0,0 +1,11 @@
+LOCAL_DIR := $(GET_LOCAL_DIR)
+
+ASM_STRING_OPS := #bcopy bzero memcpy memmove memset
+
+MODULE_SRCS += \
+	#$(LOCAL_DIR)/memcpy.S \
+	#$(LOCAL_DIR)/memset.S
+
+# filter out the C implementation
+C_STRING_OPS := $(filter-out $(ASM_STRING_OPS),$(C_STRING_OPS))
+