From 81dbfc2493a3851efe2e8fc634c00d8a9f817df6 Mon Sep 17 00:00:00 2001 From: Travis Geiselbrecht Date: Wed, 13 Aug 2014 17:22:49 -0700 Subject: [PATCH] [platform][zynq] add support for putting the base of the system in dram (1MB offset) -Add a few global #defines: ZYNQ_CODE_IN_SDRAM and ZYNQ_SDRAM_INIT which are used in a few places to initialize or not initialze dram and affect the way the VM is brought up. -Add zybo-dram-test project --- platform/zynq/platform.c | 22 ++++++++++++++++------ platform/zynq/rules.mk | 11 +++++++++-- project/zybo-dram-test.mk | 6 ++++++ target/zybo/init.c | 7 +++++++ target/zybo/rules.mk | 2 +- 5 files changed, 39 insertions(+), 9 deletions(-) create mode 100644 project/zybo-dram-test.mk diff --git a/platform/zynq/platform.c b/platform/zynq/platform.c index 6cc652b5..a66bc58e 100644 --- a/platform/zynq/platform.c +++ b/platform/zynq/platform.c @@ -40,12 +40,19 @@ __WEAK void ps7_init(void) { } STATIC_ASSERT(IS_ALIGNED(SDRAM_BASE, MB)); STATIC_ASSERT(IS_ALIGNED(SDRAM_SIZE, MB)); +#if SDRAM_SIZE != 0 +/* if we have sdram, the first 1MB is covered by sram */ +#define RAM_SIZE (MB + (SDRAM_SIZE - MB)) +#else +#define RAM_SIZE (MB) +#endif + /* initial memory mappings. parsed by start.S */ struct mmu_initial_mapping mmu_initial_mappings[] = { /* 1GB of sram + sdram space */ { .phys = SRAM_BASE, .virt = KERNEL_BASE, - .size = MB + SDRAM_SIZE - MB, + .size = RAM_SIZE, .flags = 0, .name = "memory" }, @@ -93,7 +100,7 @@ struct mmu_initial_mapping mmu_initial_mappings[] = { /* identity map to let the boot code run */ { .phys = SRAM_BASE, .virt = SRAM_BASE, - .size = MB, + .size = RAM_SIZE, .flags = MMU_INITIAL_MAPPING_TEMPORARY }, /* null entry to terminate the list */ @@ -104,7 +111,7 @@ struct mmu_initial_mapping mmu_initial_mappings[] = { static pmm_arena_t sdram_arena = { .name = "sdram", .base = SDRAM_BASE, - .size = SDRAM_SIZE - MB, + .size = SDRAM_SIZE - MB, /* first 1MB is covered by SRAM */ .flags = PMM_ARENA_FLAG_KMAP }; #endif @@ -138,16 +145,19 @@ void platform_early_init(void) arm_cortex_a9_timer_init(CPUPRIV_BASE, zynq_get_arm_timer_freq()); /* add the main memory arena */ -#if SDRAM_SIZE != 0 - /* since we have a discontinuity between the end of SRAM (256K) and the start of SDRAM (1MB), - * intentionally bump the boot-time allocator to start in the base of SDRAM. +#if !ZYNQ_CODE_IN_SDRAM && SDRAM_SIZE != 0 + /* In the case of running from SRAM, and we are using SDRAM, + * there is a discontinuity between the end of SRAM (256K) and the start of SDRAM (1MB), + * so intentionally bump the boot-time allocator to start in the base of SDRAM. */ extern uintptr_t boot_alloc_start; extern uintptr_t boot_alloc_end; boot_alloc_start = KERNEL_BASE + MB; boot_alloc_end = KERNEL_BASE + MB; +#endif +#if SDRAM_SIZE != 0 pmm_add_arena(&sdram_arena); #endif pmm_add_arena(&sram_arena); diff --git a/platform/zynq/rules.mk b/platform/zynq/rules.mk index bd666c43..0087822b 100644 --- a/platform/zynq/rules.mk +++ b/platform/zynq/rules.mk @@ -33,11 +33,18 @@ ZYNQ_SDRAM_SIZE ?= 0 ifeq ($(ZYNQ_USE_SRAM),1) MEMBASE := 0x0 MEMSIZE := 0x30000 # 3 * 64K + +GLOBAL_DEFINES += \ + ZYNQ_CODE_IN_SRAM=1 \ + ZYNQ_SDRAM_INIT=1 else -# XXX untested path MEMBASE := 0x00000000 MEMSIZE ?= $(ZYNQ_SDRAM_SIZE) # 256MB -#KERNEL_LOAD_OFFSET := 0x00100000 # loaded 1MB into physical space +KERNEL_LOAD_OFFSET := 0x00100000 # loaded 1MB into physical space + +# set a #define so system code can decide if it needs to reinitialize dram or not +GLOBAL_DEFINES += \ + ZYNQ_CODE_IN_SDRAM=1 endif # put our kernel at 0xc0000000 so we can have axi bus 1 mapped at 0x80000000 diff --git a/project/zybo-dram-test.mk b/project/zybo-dram-test.mk new file mode 100644 index 00000000..de043c40 --- /dev/null +++ b/project/zybo-dram-test.mk @@ -0,0 +1,6 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +ZYNQ_USE_SRAM := 0 + +include $(LOCAL_DIR)/zybo-test.mk + diff --git a/target/zybo/init.c b/target/zybo/init.c index 09045f6a..c8657107 100644 --- a/target/zybo/init.c +++ b/target/zybo/init.c @@ -96,6 +96,7 @@ int zynq_pll_init(void) { ARM_CLK_CTRL_CPU_3OR2XCLKACT | ARM_CLK_CTRL_CPU_2XCLKACT | ARM_CLK_CTRL_CPU_1XCLKACT |ARM_CLK_CTRL_PERI_CLKACT; +#if ZYNQ_SDRAM_INIT /* DDR PLL & Clock config * 475 cycles needed * 21 divisor on PLL @@ -113,6 +114,7 @@ int zynq_pll_init(void) { SLCR_REG(DDR_PLL_CTRL) &= ~PLL_BYPASS_FORCE; SLCR_REG(DDR_CLK_CTRL) = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT | DDR_CLK_CTRL_DDR_3XCLK_DIV(2) | DDR_CLK_CTRL_DDR_2XCLK_DIV(3); +#endif /* IO PLL config * 500 cycles needed for pll @@ -162,6 +164,8 @@ int zynq_mio_init(void) zynq_slcr_unlock(); SLCR_REG(GPIOB_CTRL) = GPIOB_CTRL_VREF_EN; + +#if ZYNQ_SDRAM_INIT SLCR_REG(DDRIOB_ADDR0) = DDRIOB_OUTPUT_EN(0x3); SLCR_REG(DDRIOB_ADDR1) = DDRIOB_OUTPUT_EN(0x3); SLCR_REG(DDRIOB_DATA0) = DDRIOB_INP_TYPE(1) | DDRIOB_TERM_EN | @@ -185,6 +189,7 @@ int zynq_mio_init(void) SLCR_REG(DDRIOB_DCI_CTRL) = 0x00000001U; SLCR_REG(DDRIOB_DCI_CTRL) |= 0x00000020U; SLCR_REG(DDRIOB_DCI_CTRL) |= 0x00000823U; +#endif /* mio pin config */ SLCR_REG(MIO_PIN_01) = MIO_L0_SEL | MIO_SPEED_FAST | MIO_IO_TYPE_LVCMOS33; @@ -576,9 +581,11 @@ int ps7_init(void) ret = zynq_clk_init(); if (ret != PS7_INIT_SUCCESS) return ret; +#if ZYNQ_SDRAM_INIT // DDR init ret = ps7_config (ps7_ddr_init_data_3_0); if (ret != PS7_INIT_SUCCESS) return ret; +#endif // Peripherals init ret = ps7_config (ps7_peripherals_init_data_3_0); diff --git a/target/zybo/rules.mk b/target/zybo/rules.mk index 44cc24b3..b9a0d2f5 100644 --- a/target/zybo/rules.mk +++ b/target/zybo/rules.mk @@ -5,7 +5,7 @@ MODULE := $(LOCAL_DIR) PLATFORM := zynq # set the system base to sram -ZYNQ_USE_SRAM := 1 +ZYNQ_USE_SRAM ?= 1 # we have sdram ZYNQ_SDRAM_SIZE := 0x10000000