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[dev][interrupt][riscv_plic] merge now 3 implementations of the same plic driver into one

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Move a copy of the PLIC driver out of one of the platforms and make the
setup of the interrupt controller a bit more dynamic.
This commit is contained in:
Travis Geiselbrecht
2023-03-09 23:09:32 -08:00
parent c66ad44efa
commit 7c2c8d8e56
19 changed files with 117 additions and 278 deletions
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7
target/qemu-sifive-u/include/platform/sifive.h
View File

@@ -10,7 +10,7 @@
#define SIFIVE_IRQ_UART0 4
#define SIFIVE_IRQ_UART1 5
#define SIFIVE_NUM_IRQS 127
#define SIFIVE_NUM_IRQS 128
#define CLINT_BASE 0x02000000
#define PLIC_BASE 0x0c000000
@@ -18,8 +18,3 @@
#define UART1_BASE 0x10011000
#define GPIO_BASE 0x10060000
#if RISCV_XMODE_OFFSET == RISCV_MACH_OFFSET
#define PLIC_HART_IDX(hart) ((hart) ? ((2 * (hart)) - 1) : 0)
#elif RISCV_XMODE_OFFSET == RISCV_SUPER_OFFSET
#define PLIC_HART_IDX(hart) ((hart) ? (2 * (hart)) : ~0U)
#endif

2
target/sifive-e/include/platform/sifive.h
View File

@@ -42,7 +42,5 @@
#define GPIO_REG_IOF_EN 14
#define GPIO_REG_IOF_SEL 15
#define PLIC_HART_IDX(hart) 0
#define GPIO_AF0 (1U << 16)
#define GPIO_AF1 (1U << 17)

6
target/sifive-unleashed/include/platform/sifive.h
View File

@@ -20,9 +20,3 @@
#define PWM0_BASE 0x10020000
#define PWM1_BASE 0x10021000
#define GPIO_BASE 0x10060000
#if RISCV_XMODE_OFFSET == RISCV_MACH_OFFSET
#define PLIC_HART_IDX(hart) ((hart) ? ((2 * (hart)) - 1) : 0)
#elif RISCV_XMODE_OFFSET == RISCV_SUPER_OFFSET
#define PLIC_HART_IDX(hart) ((hart) ? (2 * (hart)) : ~0U)
#endif