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[arch][arm] fix cache disable routines

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-Make sure the stack is kept 8 byte aligned during flush routines
-Properly save and restore cpsr during cache disable
-in PL310, spin on the control register until the disable bit sticks
This commit is contained in:
Travis Geiselbrecht
2014-08-12 16:06:18 -07:00
parent c200e71234
commit 763adc65c5
2 changed files with 11 additions and 7 deletions
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12
arch/arm/arm/cache-ops.S
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@@ -105,7 +105,7 @@ FUNCTION(arch_disable_cache)
mov r7, r0 // save flags
mrs r12, cpsr // save the old interrupt state
mrs r8, cpsr // save the old interrupt state
cpsid iaf // interrupts disabled
.Ldcache_disable:
@@ -156,16 +156,16 @@ FUNCTION(arch_disable_cache)
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 // invalidate icache to PoU
msr cpsr, r12
msr cpsr, r8
ldmfd sp!, {r4-r11, pc}
/* void arch_enable_cache(uint flags) */
FUNCTION(arch_enable_cache)
stmfd sp!, {r4-r11, lr}
stmfd sp!, {r4-r12, lr}
mov r7, r0 // save flags
mrs r12, cpsr // save the old interrupt state
mrs r8, cpsr // save the old interrupt state
cpsid iaf // interrupts disabled
.Ldcache_enable:
@@ -207,8 +207,8 @@ FUNCTION(arch_enable_cache)
mcr p15, 0, r0, c1, c0, 0 // enable icache
.Ldone_enable:
msr cpsr, r12
ldmfd sp!, {r4-r11, pc}
msr cpsr, r8
ldmfd sp!, {r4-r12, pc}
// flush & invalidate cache routine, trashes r0-r6, r9-r11
flush_invalidate_cache_v7:

6
dev/cache/pl310/pl310.c vendored
View File

@@ -124,8 +124,12 @@ status_t pl310_set_enable(bool enable)
} else {
if ((PL310_REG(REG1_CONTROL) & 1) == 1) {
/* if enabled */
PL310_REG(REG1_CONTROL) = 0;
pl310_flush_invalidate();
PL310_REG(REG1_CONTROL) = 0;
/* this seems to not always latch on the first try */
while (PL310_REG(REG1_CONTROL) & 1) {
PL310_REG(REG1_CONTROL) = 0;
}
}
}