[arch][riscv] use newly discovered pseudo-instructions for load/stores
I hadn't noticed this before, but you can directly reference a global variable in a load/store in assembly, which combines a lla + ld/sd into a 2 instruction pair instead of 3 due to the 12 bit offset provided in the load/store.
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@@ -80,8 +80,7 @@ FUNCTION(_start)
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// Save a copy of _start in physical space. This is later used
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// as the entry point for secondary cpus.
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lla t0, _start
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lla t1, _start_physical
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STR t0, (t1)
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STR t0, (_start_physical), t1
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#endif
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#if RISCV_MMU
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@@ -91,9 +90,8 @@ FUNCTION(_start)
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#if WITH_SMP
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// Release any other harts into riscv_secondary_entry
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fence w, w
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lla t1, _boot_status
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li t0, 1
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sb t0, (t1)
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sb t0, (_boot_status), t1
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fence
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#endif
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@@ -118,8 +116,7 @@ END_FUNCTION(_start)
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LOCAL_FUNCTION(secondary_trap)
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#if WITH_SMP
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// wait for _boot_status to be nonzero, then go into riscv_secondary_entry
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lla t5, _boot_status
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lb t0, (t5)
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lb t0, (_boot_status)
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beqz t0, secondary_trap
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// we've been released by the main cpu and/or we've been booted after the
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@@ -156,18 +153,15 @@ LOCAL_FUNCTION(_mmu_init)
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lla t0, trampoline_pgtable
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// store the physical address of the pgtable for future use
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lla t1, trampoline_pgtable_phys
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sd t0, (t1)
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sd t0, (trampoline_pgtable_phys), t1
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// do the same for the main kernel pgtable
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lla t2, kernel_pgtable
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lla t1, kernel_pgtable_phys
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sd t2, (t1)
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sd t2, (kernel_pgtable_phys), t1
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// and the 2nd level tables
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lla t2, kernel_l2_pgtable
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lla t1, kernel_l2_pgtable_phys
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sd t2, (t1)
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sd t2, (kernel_l2_pgtable_phys), t1
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// compute kernel pgtable pointer (index 256)
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addi t1, t0, (8 * 128)
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@@ -227,8 +221,7 @@ LOCAL_FUNCTION(_mmu_init)
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lla t1, .Lhigh
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// bounce to the high address
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lla t0, .Lhigh_addr
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ld t0, (t0)
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ld t0, (.Lhigh_addr)
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jr t0
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// the full virtual address of the .Lhigh label
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