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[riscv] switch stimecmp/stimecmph registers to using the raw integer format

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Though using the named nmemonics is a generally better idea it has the
unforunate property of not working on older compilers. In this case,
these new registers are for the Sstic extension, which is new enough
that even reasonably recent compilers as GCC 12.1 doesn't understand it.

Fixes issue #410
This commit is contained in:
Travis Geiselbrecht
2024-06-16 22:16:33 -07:00
parent 371a03357a
commit 69b8bccd76
1 changed files with 4 additions and 2 deletions
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6
arch/riscv/include/arch/riscv.h
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@@ -38,6 +38,8 @@
#define RISCV_CSR_TIMEH (0xc81)
#define RISCV_CSR_INSRETH (0xc82)
// CSRs that exist in both machine and supervisor mode. Synthesize the appropriate
// one based on prefixing the name with either m or s.
#define RISCV_CSR_XSTATUS __CONCAT(RISCV_MODE_PREFIX, status)
#define RISCV_CSR_XIE __CONCAT(RISCV_MODE_PREFIX, ie)
#define RISCV_CSR_XTVEC __CONCAT(RISCV_MODE_PREFIX, tvec)
@@ -59,8 +61,8 @@
#if RISCV_S_MODE // Supervisor-mode only CSRs
#define RISCV_CSR_SATP satp
// sstc feature
#define RISCV_CSR_STIMECMP stimecmp
#define RISCV_CSR_STIMECMPH stimecmph
#define RISCV_CSR_STIMECMP (0x14d)
#define RISCV_CSR_STIMECMPH (0x15d)
#endif
#define RISCV_CSR_XSTATUS_IE (1ul << (RISCV_XMODE_OFFSET + 0))