[ubsan] fix some bugs and warnings discovered by ubsan

- X86 cpuid feature list dump was using the wrong array and walking off
  the end of one.
- GICv2 code had a left shift by up to 31 of an integer. Needs to be
  unsigned.
- PLIC same as GIC code.
- fdtwalker code should be using a bytewise accessor based helper
  function for reading large integers out of an unaliged FDT.
- PCI BIOS32 search code could do a 32bit unaligned read of a string,
  switch to using memcmp.

dev/bus/pci/backend/bios32.cpp

@@ -82,7 +82,7 @@ static pci_bios_info *find_pci_bios_info(void) {
     uint i;
 
     while (head < (uint32_t *) (0x000ffff0 + KERNEL_BASE)) {
-        if (*head == *(uint32_t *) pci_bios_magic) {
+        if (memcmp(head, pci_bios_magic, sizeof(pci_bios_magic)) == 0) {
             // perform the checksum
             sum = 0;
             b = (int8_t *) head;

dev/interrupt/arm_gic/arm_gic.c

@@ -244,9 +244,9 @@ static status_t gic_configure_interrupt(unsigned int vector,
     uint32_t bit_shift = ((vector & 0xf) << 1) + 1;
     uint32_t reg_val   = gicreg_read32(0, GICD_ICFGR(reg_ndx));
     if (tm == IRQ_TRIGGER_MODE_EDGE) {
-        reg_val |= (1 << bit_shift);
+        reg_val |= (1U << bit_shift);
     } else {
-        reg_val &= ~(1 << bit_shift);
+        reg_val &= ~(1U << bit_shift);
     }
     gicreg_write32(0, GICD_ICFGR(reg_ndx), reg_val);
 

dev/interrupt/riscv_plic/plic.c

@@ -95,7 +95,7 @@ void plic_early_init(uintptr_t base, size_t num_irqs_, bool hart0_m_only_) {
     // mask all irqs and set their priority to 1
     // TODO: mask on all the other cpus too
     for (size_t i = 1; i < num_irqs; i++) {
-        *REG32(PLIC_ENABLE(i, riscv_current_hart())) &= ~(1 << (i % 32));
+        *REG32(PLIC_ENABLE(i, riscv_current_hart())) &= ~(1U << (i % 32));
         *REG32(PLIC_PRIORITY(i)) = 1;
     }
 
@@ -107,13 +107,13 @@ void plic_init(void) {}
 
 status_t mask_interrupt(unsigned int vector) {
     LTRACEF("vector %u, current hart %u\n", vector, riscv_current_hart());
-    *REG32(PLIC_ENABLE(vector, riscv_current_hart())) &= ~(1 << (vector % 32));
+    *REG32(PLIC_ENABLE(vector, riscv_current_hart())) &= ~(1U << (vector % 32));
     return NO_ERROR;
 }
 
 status_t unmask_interrupt(unsigned int vector) {
     LTRACEF("vector %u, current hart %u\n", vector, riscv_current_hart());
-    *REG32(PLIC_ENABLE(vector, riscv_current_hart())) |= (1 << (vector % 32));
+    *REG32(PLIC_ENABLE(vector, riscv_current_hart())) |= (1U << (vector % 32));
 
     return NO_ERROR;
 }