[arch][x86] start getting inter-processor-interrupts working
-Move the local apic driver to arch/x86 -Add routines to send IPIs between cpus Something is unstable at the moment and the system crashes after a while with random corruptions when using SMP.
This commit is contained in:
Travis Geiselbrecht
@@ -83,8 +83,6 @@ FUNCTION(setup_idt)
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loop .Lloop
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lidt _idtr
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ret
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END_FUNCTION(setup_idt)
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@@ -113,8 +113,6 @@ FUNCTION(setup_idt)
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loop .Lloop
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lidt _idtr
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ret
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END_FUNCTION(setup_idt)
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@@ -80,6 +80,9 @@ void x86_early_init_percpu(void) {
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x86_set_gdt_descriptor(selector, &system_tss, sizeof(system_tss), 1, 0, 0, SEG_TYPE_TSS, 0, 0);
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x86_ltr(selector);
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/* load the kernel's IDT */
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asm("lidt _idtr");
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x86_mmu_early_init_percpu();
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#if X86_WITH_FPU
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x86_fpu_early_init_percpu();
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26
arch/x86/include/arch/x86/lapic.h
Normal file
26
arch/x86/include/arch/x86/lapic.h
Normal file
@@ -0,0 +1,26 @@
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/*
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* Copyright (c) 2025 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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#include <platform/timer.h>
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#include <stdbool.h>
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#include <sys/types.h>
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#include <kernel/mp.h>
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// local apic
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void lapic_init(void);
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status_t lapic_timer_init(bool invariant_tsc_supported);
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void lapic_eoi(unsigned int vector);
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void lapic_send_init_ipi(uint32_t apic_id, bool level);
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void lapic_send_startup_ipi(uint32_t apic_id, uint32_t startup_vector);
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void lapic_send_ipi(uint32_t apic_id, mp_ipi_t ipi);
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status_t lapic_set_oneshot_timer(platform_timer_callback callback, void *arg, lk_time_t interval);
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void lapic_cancel_timer(void);
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@@ -16,7 +16,7 @@ typedef struct x86_percpu {
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struct x86_percpu *self;
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uint cpu_num;
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uint apic_id;
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uint32_t apic_id;
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struct thread *current_thread;
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@@ -70,10 +70,13 @@ static inline uint x86_get_cpu_num(void) {
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}
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// get the current apic id
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static inline uint x86_get_apic_id(void) {
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static inline uint32_t x86_get_apic_id(void) {
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return x86_read_gs_offset32(X86_PERCPU_FIELD_OFFSET(apic_id));
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}
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// read it from hardware directly
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uint32_t x86_get_apic_id_from_hardware(void);
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// get/set the current thread
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struct thread;
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@@ -83,4 +86,4 @@ static inline struct thread *x86_get_current_thread(void) {
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static inline void x86_set_current_thread(struct thread *t) {
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x86_write_gs_offset_ptr(X86_PERCPU_FIELD_OFFSET(current_thread), t);
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}
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}
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381
arch/x86/lapic.c
Normal file
381
arch/x86/lapic.c
Normal file
@@ -0,0 +1,381 @@
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/*
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* Copyright (c) 2021 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include "arch/x86/lapic.h"
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#include <sys/types.h>
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#include <lk/debug.h>
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#include <lk/err.h>
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#include <lk/reg.h>
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#include <lk/trace.h>
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#include <lk/init.h>
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#include <lib/fixed_point.h>
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#include <assert.h>
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#include <kernel/thread.h>
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#include <platform/interrupts.h>
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#include <arch/ops.h>
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#include <arch/x86.h>
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#include <arch/x86/feature.h>
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#include <kernel/spinlock.h>
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#include <platform/time.h>
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#include <platform/timer.h>
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#include <platform/pc/timer.h>
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#include <kernel/vm.h>
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#include <kernel/mp.h>
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#define LOCAL_TRACE 0
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static bool lapic_present = false;
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static bool lapic_x2apic = false;
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static bool use_tsc_deadline = false;
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static volatile uint32_t *lapic_mmio;
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static struct fp_32_64 timebase_to_lapic;
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// TODO: move these callbacks into the shared timer code
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static platform_timer_callback t_callback;
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static void *callback_arg;
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static void lapic_init_percpu(uint level);
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// local apic registers
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enum lapic_regs {
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LAPIC_ID = 0x20,
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LAPIC_VERSION = 0x30,
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LAPIC_TPR = 0x80,
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LAPIC_APR = 0x90,
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LAPIC_PPR = 0xa0,
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LAPIC_EOI = 0xb0,
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LAPIC_RRD = 0xc0,
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LAPIC_LDR = 0xd0,
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LAPIC_DFR = 0xe0,
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LAPIC_SVR = 0xf0,
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LAPIC_ISR0 = 0x100,
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LAPIC_TMR0 = 0x180,
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LAPIC_IRR0 = 0x200,
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LAPIC_ESR = 0x280,
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LAPIC_CMCI = 0x2f0,
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LAPIC_ICRLO = 0x300,
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LAPIC_ICRHI = 0x310,
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LAPIC_TIMER = 0x320,
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LAPIC_THERMAL = 0x330,
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LAPIC_PERF = 0x340,
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LAPIC_LINT0 = 0x350,
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LAPIC_LINT1 = 0x360,
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LAPIC_ERROR = 0x370,
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LAPIC_TICR = 0x380,
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LAPIC_TCCR = 0x390,
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LAPIC_DIV = 0x3e0,
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// Extended features
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LAPIC_EXT_FEATURES = 0x400,
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LAPIC_EXT_CONTROL = 0x410,
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LAPIC_EXT_SEOI = 0x420,
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LAPIC_EXT_IER0 = 0x480,
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LAPIC_EXT_LVT0 = 0x500,
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};
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enum lapic_interrupts {
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LAPIC_INT_TIMER = 0xf8,
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LAPIC_INT_SPURIOUS,
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LAPIC_INT_GENERIC,
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LAPIC_INT_RESCHEDULE,
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};
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enum lapic_timer_mode {
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LAPIC_TIMER_MODE_ONESHOT = 0,
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LAPIC_TIMER_MODE_PERIODIC = 1,
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LAPIC_TIMER_MODE_TSC_DEADLINE = 2,
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};
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static uint32_t lapic_read(enum lapic_regs reg) {
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LTRACEF_LEVEL(2, "reg %#x\n", reg);
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DEBUG_ASSERT(reg != LAPIC_ICRLO && reg != LAPIC_ICRHI);
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if (lapic_x2apic) {
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// TODO: do we need barriers here?
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return read_msr(X86_MSR_IA32_X2APIC_BASE + reg / 0x10);
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} else {
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return mmio_read32(lapic_mmio + reg / 4);
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}
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}
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static void lapic_write(enum lapic_regs reg, uint32_t val) {
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LTRACEF_LEVEL(2, "reg %#x val %#x\n", reg, val);
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DEBUG_ASSERT(reg != LAPIC_ICRLO && reg != LAPIC_ICRHI);
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if (lapic_x2apic) {
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write_msr(X86_MSR_IA32_X2APIC_BASE + reg / 0x10, val);
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} else {
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mmio_write32(lapic_mmio + reg / 4, val);
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}
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}
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// special case to write to the ICR register
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static void lapic_write_icr(uint32_t low, uint32_t apic_id) {
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LTRACEF_LEVEL(2, "%#x apic_id %#x\n", low, apic_id);
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if (lapic_x2apic) {
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write_msr(X86_MSR_IA32_X2APIC_BASE + 0x30, ((uint64_t)apic_id << 32) | low);
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} else {
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lapic_write(LAPIC_ICRHI, apic_id << 24);
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lapic_write(LAPIC_ICRLO, low);
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}
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}
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status_t lapic_set_oneshot_timer(platform_timer_callback callback, void *arg, lk_time_t interval) {
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LTRACEF("cpu %u interval %u\n", arch_curr_cpu_num(), interval);
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DEBUG_ASSERT(arch_ints_disabled());
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t_callback = callback;
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callback_arg = arg;
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if (use_tsc_deadline) {
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uint64_t now = __builtin_ia32_rdtsc();
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uint64_t delta = time_to_tsc_ticks(interval);
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uint64_t deadline = now + delta;
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LTRACEF("now %llu delta %llu deadline %llu\n", now, delta, deadline);
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write_msr(X86_MSR_IA32_TSC_DEADLINE, deadline);
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} else {
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// set the initial count, which should trigger the timer
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uint64_t ticks = u64_mul_u32_fp32_64(interval, timebase_to_lapic);
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if (ticks > UINT32_MAX) {
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ticks = UINT32_MAX;
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}
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lapic_write(LAPIC_TICR, ticks & 0xffffffff);
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}
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return NO_ERROR;
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}
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void lapic_cancel_timer(void) {
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LTRACE;
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DEBUG_ASSERT(arch_ints_disabled());
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if (use_tsc_deadline) {
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write_msr(X86_MSR_IA32_TSC_DEADLINE, 0);
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} else {
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lapic_write(LAPIC_TICR, 0);
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}
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}
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static enum handler_return lapic_timer_handler(void *arg) {
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LTRACEF("cpu %u\n", arch_curr_cpu_num());
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enum handler_return ret = INT_NO_RESCHEDULE;
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if (t_callback) {
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ret = t_callback(callback_arg, current_time());
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}
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return ret;
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}
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static enum handler_return lapic_spurious_handler(void *arg) {
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LTRACEF("cpu %u, arg %p\n", arch_curr_cpu_num(), arg);
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return INT_NO_RESCHEDULE;
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}
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static enum handler_return lapic_generic_handler(void *arg) {
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LTRACEF("cpu %u, arg %p\n", arch_curr_cpu_num(), arg);
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return INT_NO_RESCHEDULE;
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}
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static enum handler_return lapic_reschedule_handler(void *arg) {
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LTRACEF("cpu %u, arg %p\n", arch_curr_cpu_num(), arg);
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return mp_mbx_reschedule_irq();
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}
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void lapic_init(void) {
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lapic_present = x86_feature_test(X86_FEATURE_APIC);
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}
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static void lapic_init_postvm(uint level) {
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if (!lapic_present) {
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return;
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}
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dprintf(INFO, "X86: local apic detected\n");
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// IA32_APIC_BASE_MSR
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uint64_t apic_base = read_msr(X86_MSR_IA32_APIC_BASE);
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LTRACEF("raw apic base msr %#llx\n", apic_base);
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// make sure it's enabled
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if ((apic_base & (1u<<11)) == 0) {
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dprintf(INFO, "X86: enabling lapic\n");
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apic_base |= (1u<<11);
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write_msr(X86_MSR_IA32_APIC_BASE, apic_base);
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}
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dprintf(INFO, "X86: lapic physical address %#llx\n", apic_base & ~0xfff);
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// see if x2APIC mode is supported and enable
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if (x86_feature_test(X86_FEATURE_X2APIC)) {
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lapic_x2apic = true;
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dprintf(INFO, "X86: local apic supports x2APIC mode\n");
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write_msr(X86_MSR_IA32_APIC_BASE, apic_base | (1u<<10));
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}
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// map the lapic into the kernel since it's not guaranteed that the physmap covers it
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if (!lapic_mmio) {
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LTRACEF("mapping lapic into kernel\n");
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status_t err = vmm_alloc_physical(vmm_get_kernel_aspace(), "lapic", PAGE_SIZE, (void **)&lapic_mmio, 0,
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apic_base & ~0xfff, /* vmm_flags */ 0, ARCH_MMU_FLAG_UNCACHED_DEVICE);
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ASSERT(err == NO_ERROR);
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}
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// Read the local apic id and version and features
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uint32_t id = lapic_read(LAPIC_ID);
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uint32_t version = lapic_read(LAPIC_VERSION);
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bool eas = version & (1u<<31);
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uint32_t max_lvt = (version >> 16) & 0xff;
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version &= 0xff;
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dprintf(INFO, "X86: local apic id %#x version %#x\n", id, version);
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dprintf(INFO, "X86: local apic max lvt entries %u\n", max_lvt);
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if (eas) {
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dprintf(INFO, "X86: local apic EAS features %#x\n", lapic_read(LAPIC_EXT_FEATURES));
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}
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// Finish up some local initialization that all cpus will want to do
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lapic_init_percpu(0);
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}
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LK_INIT_HOOK(lapic_init_postvm, lapic_init_postvm, LK_INIT_LEVEL_VM + 1);
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static void lapic_init_percpu(uint level) {
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// Make sure the apic is enabled and x2apic mode is set (if supported)
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uint64_t apic_base = read_msr(X86_MSR_IA32_APIC_BASE);
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apic_base |= (1u<<11);
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if (lapic_x2apic) {
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apic_base |= (1u<<10);
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}
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write_msr(X86_MSR_IA32_APIC_BASE, apic_base);
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// set the spurious vector register
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uint32_t svr = (LAPIC_INT_SPURIOUS | (1u<<8)); // enable
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lapic_write(LAPIC_SVR, svr);
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TRACEF("lapic svr %#x\n", lapic_read(LAPIC_SVR));
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register_int_handler_msi(LAPIC_INT_SPURIOUS, &lapic_spurious_handler, NULL, false);
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register_int_handler_msi(LAPIC_INT_GENERIC, &lapic_generic_handler, NULL, false);
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register_int_handler_msi(LAPIC_INT_RESCHEDULE, &lapic_reschedule_handler, NULL, false);
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}
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LK_INIT_HOOK_FLAGS(lapic_init_percpu, lapic_init_percpu, LK_INIT_LEVEL_VM, LK_INIT_FLAG_SECONDARY_CPUS);
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static uint32_t lapic_read_current_tick(void) {
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if (!lapic_present) {
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return 0;
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}
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return lapic_read(LAPIC_TCCR);
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}
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static void lapic_timer_init_percpu(uint level) {
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// check for deadline mode
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if (use_tsc_deadline) {
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// put the timer in TSC deadline and clear the match register
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uint32_t val = (LAPIC_TIMER_MODE_TSC_DEADLINE << 17) | LAPIC_INT_TIMER;
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lapic_write(LAPIC_TIMER, val);
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write_msr(X86_MSR_IA32_TSC_DEADLINE, 0);
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} else {
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// configure the local timer and make sure it is not set to fire
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uint32_t val = (LAPIC_TIMER_MODE_ONESHOT << 17) | LAPIC_INT_TIMER;
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lapic_write(LAPIC_TIMER, val);
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lapic_write(LAPIC_TICR, 0);
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}
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// register the timer interrupt vector
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register_int_handler_msi(LAPIC_INT_TIMER, &lapic_timer_handler, NULL, false);
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}
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LK_INIT_HOOK_FLAGS(lapic_timer_init_percpu, lapic_timer_init_percpu, LK_INIT_LEVEL_VM + 1, LK_INIT_FLAG_SECONDARY_CPUS);
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status_t lapic_timer_init(bool invariant_tsc_supported) {
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if (!lapic_present) {
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return ERR_NOT_FOUND;
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}
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// check for deadline mode
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bool tsc_deadline = x86_feature_test(X86_FEATURE_TSC_DEADLINE);
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if (invariant_tsc_supported && tsc_deadline) {
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dprintf(INFO, "X86: local apic timer supports TSC deadline mode\n");
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use_tsc_deadline = true;
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} else {
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// configure the local timer and make sure it is not set to fire
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uint32_t val = (LAPIC_TIMER_MODE_ONESHOT << 17) | LAPIC_INT_TIMER;
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lapic_write(LAPIC_TIMER, val);
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// calibrate the timer frequency
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lapic_write(LAPIC_TICR, 0xffffffff); // countdown from the max count
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uint32_t lapic_hz = pit_calibrate_lapic(&lapic_read_current_tick);
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lapic_write(LAPIC_TICR, 0);
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printf("X86: local apic timer frequency %uHz\n", lapic_hz);
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fp_32_64_div_32_32(&timebase_to_lapic, lapic_hz, 1000);
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dprintf(INFO, "X86: timebase to local apic timer ratio %u.%08u...\n",
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timebase_to_lapic.l0, timebase_to_lapic.l32);
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}
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lapic_timer_init_percpu(0);
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return NO_ERROR;
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}
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void lapic_eoi(unsigned int vector) {
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LTRACEF("vector %#x\n", vector);
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if (!lapic_present) {
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return;
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}
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|
||||
lapic_write(LAPIC_EOI, 0);
|
||||
}
|
||||
|
||||
void lapic_send_init_ipi(uint32_t apic_id, bool level) {
|
||||
if (!lapic_present) {
|
||||
return;
|
||||
}
|
||||
|
||||
lapic_write_icr((5u << 8) | (level ? (1u << 14) : 0), apic_id);
|
||||
}
|
||||
|
||||
void lapic_send_startup_ipi(uint32_t apic_id, uint32_t startup_vector) {
|
||||
if (!lapic_present) {
|
||||
return;
|
||||
}
|
||||
|
||||
lapic_write_icr((6u << 8) | (startup_vector >> 12), apic_id);
|
||||
}
|
||||
|
||||
void lapic_send_ipi(uint32_t apic_id, mp_ipi_t ipi) {
|
||||
if (!lapic_present) {
|
||||
return;
|
||||
}
|
||||
|
||||
LTRACEF("cpu %u target apic_id %#x, ipi %u\n", arch_curr_cpu_num(), apic_id, ipi);
|
||||
|
||||
uint32_t vector;
|
||||
switch (ipi) {
|
||||
case MP_IPI_GENERIC:
|
||||
vector = LAPIC_INT_GENERIC;
|
||||
break;
|
||||
case MP_IPI_RESCHEDULE:
|
||||
vector = LAPIC_INT_RESCHEDULE;
|
||||
break;
|
||||
default:
|
||||
panic("X86: unknown IPI %u\n", ipi);
|
||||
}
|
||||
|
||||
// send fixed mode, level asserted, no destination shorthand interrupt
|
||||
lapic_write_icr(vector | (1U << 14), apic_id);
|
||||
}
|
||||
@@ -18,8 +18,9 @@
|
||||
#include <arch/x86/descriptor.h>
|
||||
#include <arch/arch_ops.h>
|
||||
#include <sys/types.h>
|
||||
#include <arch/x86/lapic.h>
|
||||
|
||||
#define LOCAL_TRACE 1
|
||||
#define LOCAL_TRACE 0
|
||||
|
||||
#if WITH_SMP
|
||||
|
||||
@@ -58,30 +59,56 @@ void x86_configure_percpu_early(uint cpu_num, uint apic_id) {
|
||||
}
|
||||
|
||||
status_t arch_mp_send_ipi(mp_cpu_mask_t target, mp_ipi_t ipi) {
|
||||
LTRACEF("caller %#x target 0x%x, ipi 0x%x\n", arch_curr_cpu_num(), target, ipi);
|
||||
LTRACEF("cpu %u target 0x%x, ipi 0x%x\n", arch_curr_cpu_num(), target, ipi);
|
||||
|
||||
// XXX call into local apic code to send IPI
|
||||
DEBUG_ASSERT(arch_ints_disabled());
|
||||
uint curr_cpu_num = arch_curr_cpu_num();
|
||||
|
||||
PANIC_UNIMPLEMENTED;
|
||||
// translate the target bitmap to apic id
|
||||
while (target) {
|
||||
uint cpu_num = __builtin_ctz(target);
|
||||
target &= ~(1u << cpu_num);
|
||||
|
||||
// skip the current cpu
|
||||
if (cpu_num == curr_cpu_num) {
|
||||
continue;
|
||||
}
|
||||
|
||||
x86_percpu_t *percpu = x86_get_percpu_for_cpu(cpu_num);
|
||||
uint32_t apic_id = percpu->apic_id;
|
||||
|
||||
// send the ipi to the target cpu
|
||||
lapic_send_ipi(apic_id, ipi);
|
||||
}
|
||||
|
||||
return NO_ERROR;
|
||||
}
|
||||
|
||||
void arch_mp_init_percpu(void) {
|
||||
}
|
||||
|
||||
static uintptr_t x86_get_apic_id_from_hardware(void) {
|
||||
// read the apic id out of the hardware
|
||||
return read_msr(X86_MSR_IA32_APIC_BASE) >> 24;
|
||||
uint32_t x86_get_apic_id_from_hardware(void) {
|
||||
// read the apic id out of cpuid leaf 1, which should be present if SMP is enabled.
|
||||
uint32_t apic_id, unused;
|
||||
cpuid(0x1, &unused, &apic_id, &unused, &unused);
|
||||
|
||||
apic_id >>= 24;
|
||||
|
||||
// TODO: read full 32bit apic id from x2apic msr if available
|
||||
|
||||
return apic_id;
|
||||
}
|
||||
|
||||
void x86_secondary_entry(uint cpu_num) {
|
||||
x86_configure_percpu_early(cpu_num, x86_get_apic_id_from_hardware());
|
||||
uint32_t apic_id = x86_get_apic_id_from_hardware();
|
||||
x86_configure_percpu_early(cpu_num, apic_id);
|
||||
|
||||
x86_early_init_percpu();
|
||||
|
||||
// run early secondary cpu init routines up to the threading level
|
||||
lk_init_level(LK_INIT_FLAG_SECONDARY_CPUS, LK_INIT_LEVEL_EARLIEST, LK_INIT_LEVEL_THREADING - 1);
|
||||
|
||||
dprintf(INFO, "SMP: secondary cpu %u started\n", arch_curr_cpu_num());
|
||||
dprintf(INFO, "SMP: secondary cpu %u started, apic id %u\n", arch_curr_cpu_num(), apic_id);
|
||||
|
||||
lk_secondary_cpu_entry();
|
||||
|
||||
|
||||
7
arch/x86/pv.c
Normal file
7
arch/x86/pv.c
Normal file
@@ -0,0 +1,7 @@
|
||||
/*
|
||||
* Copyright (c) 2025 Travis Geiselbrecht
|
||||
*
|
||||
* Use of this source code is governed by a MIT-style
|
||||
* license that can be found in the LICENSE file or at
|
||||
* https://opensource.org/licenses/MIT
|
||||
*/
|
||||
@@ -3,6 +3,7 @@ LOCAL_DIR := $(GET_LOCAL_DIR)
|
||||
MODULE := $(LOCAL_DIR)
|
||||
|
||||
MODULE_OPTIONS := extra_warnings
|
||||
MODULE_DEPS := lib/fixed_point
|
||||
|
||||
# x86 code always runs with the mmu enabled
|
||||
WITH_KERNEL_VM := 1
|
||||
@@ -74,7 +75,9 @@ MODULE_SRCS += \
|
||||
$(LOCAL_DIR)/descriptor.c \
|
||||
$(LOCAL_DIR)/faults.c \
|
||||
$(LOCAL_DIR)/feature.c \
|
||||
$(LOCAL_DIR)/lapic.c \
|
||||
$(LOCAL_DIR)/mp.c \
|
||||
$(LOCAL_DIR)/pv.c \
|
||||
$(LOCAL_DIR)/thread.c \
|
||||
|
||||
# legacy x86's dont have fpu support
|
||||
|
||||
Reference in New Issue
Block a user