[arch][arm][arm-m] Implement arch_in_int_handler for ARM-M V7 CPUs

arch/arm/include/arch/arch_ops.h

@@ -29,6 +29,10 @@
 #include <reg.h>
 #include <arch/arm.h>
 
+#if ARM_ISA_ARMV7M
+#include <arch/arm/cm.h>
+#endif
+
 __BEGIN_CDECLS;
 
 #if ARM_ISA_ARMV7 || (ARM_ISA_ARMV6 && !__thumb__)
@@ -87,10 +91,16 @@ static inline bool arch_fiqs_disabled(void)
 
 static inline bool arch_in_int_handler(void)
 {
+#if ARM_ISA_ARMV7M
+    uint32_t ipsr;
+    __asm volatile ("MRS %0, ipsr" : "=r" (ipsr) );
+    return (ipsr & IPSR_ISR_Msk);
+#else
     /* set by the interrupt glue to track that the cpu is inside a handler */
     extern bool __arm_in_handler;
 
     return __arm_in_handler;
+#endif
 }
 
 static inline int atomic_add(volatile int *ptr, int val)