[platform][stellaris] create a more standard vectab
This commit is contained in:
Travis Geiselbrecht
@@ -31,7 +31,7 @@ MODULE_SRCS += \
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$(LOCAL_DIR)/init.c \
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$(LOCAL_DIR)/debug.c \
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$(LOCAL_DIR)/timer.c \
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$(LOCAL_DIR)/startup_gcc.c \
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$(LOCAL_DIR)/vectab.c \
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# $(LOCAL_DIR)/debug.c \
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@@ -1,201 +0,0 @@
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//*****************************************************************************
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//
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// startup_gcc.c - Startup code for use with GNU tools.
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//
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// Copyright (c) 2012 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 9453 of the EK-LM4F120XL Firmware Package.
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//
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//*****************************************************************************
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#include "inc/hw_nvic.h"
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#include "inc/hw_types.h"
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//*****************************************************************************
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//
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// Forward declaration of the default fault handlers.
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//
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//*****************************************************************************
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static void IntDefaultHandler(void);
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extern void stellaris_uart_irq(void);
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//*****************************************************************************
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//
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// The vector table. Note that the proper constructs must be placed on this to
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// ensure that it ends up at physical address 0x0000.0000.
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//
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//*****************************************************************************
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__attribute__ ((section(".text.boot.vectab2")))
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void (* const g_pfnVectors[])(void) = {
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IntDefaultHandler, // GPIO Port A
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IntDefaultHandler, // GPIO Port B
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IntDefaultHandler, // GPIO Port C
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IntDefaultHandler, // GPIO Port D
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IntDefaultHandler, // GPIO Port E
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stellaris_uart_irq, // UART0 Rx and Tx
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IntDefaultHandler, // UART1 Rx and Tx
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IntDefaultHandler, // SSI0 Rx and Tx
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IntDefaultHandler, // I2C0 Master and Slave
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IntDefaultHandler, // PWM Fault
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IntDefaultHandler, // PWM Generator 0
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IntDefaultHandler, // PWM Generator 1
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IntDefaultHandler, // PWM Generator 2
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IntDefaultHandler, // Quadrature Encoder 0
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IntDefaultHandler, // ADC Sequence 0
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IntDefaultHandler, // ADC Sequence 1
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IntDefaultHandler, // ADC Sequence 2
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IntDefaultHandler, // ADC Sequence 3
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IntDefaultHandler, // Watchdog timer
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IntDefaultHandler, // Timer 0 subtimer A
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IntDefaultHandler, // Timer 0 subtimer B
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IntDefaultHandler, // Timer 1 subtimer A
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IntDefaultHandler, // Timer 1 subtimer B
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IntDefaultHandler, // Timer 2 subtimer A
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IntDefaultHandler, // Timer 2 subtimer B
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IntDefaultHandler, // Analog Comparator 0
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IntDefaultHandler, // Analog Comparator 1
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IntDefaultHandler, // Analog Comparator 2
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IntDefaultHandler, // System Control (PLL, OSC, BO)
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IntDefaultHandler, // FLASH Control
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IntDefaultHandler, // GPIO Port F
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IntDefaultHandler, // GPIO Port G
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IntDefaultHandler, // GPIO Port H
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IntDefaultHandler, // UART2 Rx and Tx
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IntDefaultHandler, // SSI1 Rx and Tx
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IntDefaultHandler, // Timer 3 subtimer A
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IntDefaultHandler, // Timer 3 subtimer B
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IntDefaultHandler, // I2C1 Master and Slave
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IntDefaultHandler, // Quadrature Encoder 1
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IntDefaultHandler, // CAN0
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IntDefaultHandler, // CAN1
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IntDefaultHandler, // CAN2
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IntDefaultHandler, // Ethernet
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IntDefaultHandler, // Hibernate
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IntDefaultHandler, // USB0
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IntDefaultHandler, // PWM Generator 3
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IntDefaultHandler, // uDMA Software Transfer
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IntDefaultHandler, // uDMA Error
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IntDefaultHandler, // ADC1 Sequence 0
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IntDefaultHandler, // ADC1 Sequence 1
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IntDefaultHandler, // ADC1 Sequence 2
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IntDefaultHandler, // ADC1 Sequence 3
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IntDefaultHandler, // I2S0
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IntDefaultHandler, // External Bus Interface 0
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IntDefaultHandler, // GPIO Port J
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IntDefaultHandler, // GPIO Port K
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IntDefaultHandler, // GPIO Port L
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IntDefaultHandler, // SSI2 Rx and Tx
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IntDefaultHandler, // SSI3 Rx and Tx
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IntDefaultHandler, // UART3 Rx and Tx
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IntDefaultHandler, // UART4 Rx and Tx
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IntDefaultHandler, // UART5 Rx and Tx
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IntDefaultHandler, // UART6 Rx and Tx
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IntDefaultHandler, // UART7 Rx and Tx
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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IntDefaultHandler, // I2C2 Master and Slave
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IntDefaultHandler, // I2C3 Master and Slave
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IntDefaultHandler, // Timer 4 subtimer A
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IntDefaultHandler, // Timer 4 subtimer B
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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IntDefaultHandler, // Timer 5 subtimer A
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IntDefaultHandler, // Timer 5 subtimer B
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IntDefaultHandler, // Wide Timer 0 subtimer A
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IntDefaultHandler, // Wide Timer 0 subtimer B
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IntDefaultHandler, // Wide Timer 1 subtimer A
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IntDefaultHandler, // Wide Timer 1 subtimer B
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IntDefaultHandler, // Wide Timer 2 subtimer A
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IntDefaultHandler, // Wide Timer 2 subtimer B
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IntDefaultHandler, // Wide Timer 3 subtimer A
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IntDefaultHandler, // Wide Timer 3 subtimer B
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IntDefaultHandler, // Wide Timer 4 subtimer A
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IntDefaultHandler, // Wide Timer 4 subtimer B
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IntDefaultHandler, // Wide Timer 5 subtimer A
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IntDefaultHandler, // Wide Timer 5 subtimer B
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IntDefaultHandler, // FPU
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IntDefaultHandler, // PECI 0
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IntDefaultHandler, // LPC 0
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IntDefaultHandler, // I2C4 Master and Slave
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IntDefaultHandler, // I2C5 Master and Slave
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IntDefaultHandler, // GPIO Port M
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IntDefaultHandler, // GPIO Port N
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IntDefaultHandler, // Quadrature Encoder 2
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IntDefaultHandler, // Fan 0
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0, // Reserved
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IntDefaultHandler, // GPIO Port P (Summary or P0)
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IntDefaultHandler, // GPIO Port P1
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IntDefaultHandler, // GPIO Port P2
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IntDefaultHandler, // GPIO Port P3
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IntDefaultHandler, // GPIO Port P4
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IntDefaultHandler, // GPIO Port P5
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IntDefaultHandler, // GPIO Port P6
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IntDefaultHandler, // GPIO Port P7
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IntDefaultHandler, // GPIO Port Q (Summary or Q0)
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IntDefaultHandler, // GPIO Port Q1
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IntDefaultHandler, // GPIO Port Q2
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IntDefaultHandler, // GPIO Port Q3
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IntDefaultHandler, // GPIO Port Q4
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IntDefaultHandler, // GPIO Port Q5
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IntDefaultHandler, // GPIO Port Q6
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IntDefaultHandler, // GPIO Port Q7
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IntDefaultHandler, // GPIO Port R
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IntDefaultHandler, // GPIO Port S
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IntDefaultHandler, // PWM 1 Generator 0
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IntDefaultHandler, // PWM 1 Generator 1
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IntDefaultHandler, // PWM 1 Generator 2
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IntDefaultHandler, // PWM 1 Generator 3
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IntDefaultHandler // PWM 1 Fault
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};
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//*****************************************************************************
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//
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// This is the code that gets called when the processor receives an unexpected
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// interrupt. This simply enters an infinite loop, preserving the system state
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// for examination by a debugger.
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//
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//*****************************************************************************
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static void
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IntDefaultHandler(void)
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{
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//
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// Go into an infinite loop.
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//
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while (1) {
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}
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}
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179
platform/stellaris/vectab.c
Normal file
179
platform/stellaris/vectab.c
Normal file
@@ -0,0 +1,179 @@
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/*
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* Copyright (c) 2013 Travis Geiselbrecht
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files
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* (the "Software"), to deal in the Software without restriction,
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* including without limitation the rights to use, copy, modify, merge,
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* publish, distribute, sublicense, and/or sell copies of the Software,
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* and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <debug.h>
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#include <compiler.h>
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#include <arch/arm/cm.h>
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/* un-overridden irq handler */
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void stellaris_dummy_irq(void)
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{
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arm_cm_irq_entry();
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panic("unhandled irq\n");
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}
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extern void stellaris_uart_irq(void);
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const void * const __SECTION(".text.boot.vectab2") vectab2[] = {
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stellaris_dummy_irq, // GPIO Port A
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stellaris_dummy_irq, // GPIO Port B
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stellaris_dummy_irq, // GPIO Port C
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stellaris_dummy_irq, // GPIO Port D
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stellaris_dummy_irq, // GPIO Port E
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stellaris_uart_irq, // UART0 Rx and Tx
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stellaris_dummy_irq, // UART1 Rx and Tx
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stellaris_dummy_irq, // SSI0 Rx and Tx
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stellaris_dummy_irq, // I2C0 Master and Slave
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stellaris_dummy_irq, // PWM Fault
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stellaris_dummy_irq, // PWM Generator 0
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stellaris_dummy_irq, // PWM Generator 1
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stellaris_dummy_irq, // PWM Generator 2
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stellaris_dummy_irq, // Quadrature Encoder 0
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stellaris_dummy_irq, // ADC Sequence 0
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stellaris_dummy_irq, // ADC Sequence 1
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stellaris_dummy_irq, // ADC Sequence 2
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stellaris_dummy_irq, // ADC Sequence 3
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stellaris_dummy_irq, // Watchdog timer
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stellaris_dummy_irq, // Timer 0 subtimer A
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stellaris_dummy_irq, // Timer 0 subtimer B
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stellaris_dummy_irq, // Timer 1 subtimer A
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stellaris_dummy_irq, // Timer 1 subtimer B
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stellaris_dummy_irq, // Timer 2 subtimer A
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stellaris_dummy_irq, // Timer 2 subtimer B
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stellaris_dummy_irq, // Analog Comparator 0
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stellaris_dummy_irq, // Analog Comparator 1
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stellaris_dummy_irq, // Analog Comparator 2
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stellaris_dummy_irq, // System Control (PLL, OSC, BO)
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stellaris_dummy_irq, // FLASH Control
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stellaris_dummy_irq, // GPIO Port F
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stellaris_dummy_irq, // GPIO Port G
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stellaris_dummy_irq, // GPIO Port H
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stellaris_dummy_irq, // UART2 Rx and Tx
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stellaris_dummy_irq, // SSI1 Rx and Tx
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stellaris_dummy_irq, // Timer 3 subtimer A
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stellaris_dummy_irq, // Timer 3 subtimer B
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stellaris_dummy_irq, // I2C1 Master and Slave
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stellaris_dummy_irq, // Quadrature Encoder 1
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stellaris_dummy_irq, // CAN0
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stellaris_dummy_irq, // CAN1
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stellaris_dummy_irq, // CAN2
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stellaris_dummy_irq, // Ethernet
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stellaris_dummy_irq, // Hibernate
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stellaris_dummy_irq, // USB0
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stellaris_dummy_irq, // PWM Generator 3
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stellaris_dummy_irq, // uDMA Software Transfer
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stellaris_dummy_irq, // uDMA Error
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stellaris_dummy_irq, // ADC1 Sequence 0
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stellaris_dummy_irq, // ADC1 Sequence 1
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stellaris_dummy_irq, // ADC1 Sequence 2
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stellaris_dummy_irq, // ADC1 Sequence 3
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stellaris_dummy_irq, // I2S0
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stellaris_dummy_irq, // External Bus Interface 0
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stellaris_dummy_irq, // GPIO Port J
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stellaris_dummy_irq, // GPIO Port K
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stellaris_dummy_irq, // GPIO Port L
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stellaris_dummy_irq, // SSI2 Rx and Tx
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stellaris_dummy_irq, // SSI3 Rx and Tx
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stellaris_dummy_irq, // UART3 Rx and Tx
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stellaris_dummy_irq, // UART4 Rx and Tx
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stellaris_dummy_irq, // UART5 Rx and Tx
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stellaris_dummy_irq, // UART6 Rx and Tx
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stellaris_dummy_irq, // UART7 Rx and Tx
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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stellaris_dummy_irq, // I2C2 Master and Slave
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stellaris_dummy_irq, // I2C3 Master and Slave
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stellaris_dummy_irq, // Timer 4 subtimer A
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stellaris_dummy_irq, // Timer 4 subtimer B
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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stellaris_dummy_irq, // Timer 5 subtimer A
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stellaris_dummy_irq, // Timer 5 subtimer B
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stellaris_dummy_irq, // Wide Timer 0 subtimer A
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stellaris_dummy_irq, // Wide Timer 0 subtimer B
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stellaris_dummy_irq, // Wide Timer 1 subtimer A
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stellaris_dummy_irq, // Wide Timer 1 subtimer B
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stellaris_dummy_irq, // Wide Timer 2 subtimer A
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stellaris_dummy_irq, // Wide Timer 2 subtimer B
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stellaris_dummy_irq, // Wide Timer 3 subtimer A
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stellaris_dummy_irq, // Wide Timer 3 subtimer B
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stellaris_dummy_irq, // Wide Timer 4 subtimer A
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stellaris_dummy_irq, // Wide Timer 4 subtimer B
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stellaris_dummy_irq, // Wide Timer 5 subtimer A
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stellaris_dummy_irq, // Wide Timer 5 subtimer B
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stellaris_dummy_irq, // FPU
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stellaris_dummy_irq, // PECI 0
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stellaris_dummy_irq, // LPC 0
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stellaris_dummy_irq, // I2C4 Master and Slave
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stellaris_dummy_irq, // I2C5 Master and Slave
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stellaris_dummy_irq, // GPIO Port M
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stellaris_dummy_irq, // GPIO Port N
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stellaris_dummy_irq, // Quadrature Encoder 2
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stellaris_dummy_irq, // Fan 0
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0, // Reserved
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stellaris_dummy_irq, // GPIO Port P (Summary or P0)
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stellaris_dummy_irq, // GPIO Port P1
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stellaris_dummy_irq, // GPIO Port P2
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stellaris_dummy_irq, // GPIO Port P3
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stellaris_dummy_irq, // GPIO Port P4
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stellaris_dummy_irq, // GPIO Port P5
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stellaris_dummy_irq, // GPIO Port P6
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stellaris_dummy_irq, // GPIO Port P7
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stellaris_dummy_irq, // GPIO Port Q (Summary or Q0)
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stellaris_dummy_irq, // GPIO Port Q1
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stellaris_dummy_irq, // GPIO Port Q2
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stellaris_dummy_irq, // GPIO Port Q3
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stellaris_dummy_irq, // GPIO Port Q4
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stellaris_dummy_irq, // GPIO Port Q5
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stellaris_dummy_irq, // GPIO Port Q6
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stellaris_dummy_irq, // GPIO Port Q7
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stellaris_dummy_irq, // GPIO Port R
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stellaris_dummy_irq, // GPIO Port S
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stellaris_dummy_irq, // PWM 1 Generator 0
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stellaris_dummy_irq, // PWM 1 Generator 1
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stellaris_dummy_irq, // PWM 1 Generator 2
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stellaris_dummy_irq, // PWM 1 Generator 3
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stellaris_dummy_irq // PWM 1 Fault
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};
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