lby/lk
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[riscv][clang] Use a CSR name instead of a numeric expression

Browse Source 
Clang's assembler rejects expressions containing e.g. (1u << N) in the
assembler. Instead using numeric expressions for per-privilege level
CSRs, we can prepend `m` or `s`. This also lets the compiler assign the
CSR encoding instead of having to hardcode it in the source code.
This commit is contained in:
Alex Richardson
2021-12-09 11:14:22 +00:00
parent 6025bec3a1
commit 496e2f4b8c
4 changed files with 14 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
arch/riscv/include/arch/riscv.h
View File

@@ -19,9 +19,11 @@
#if RISCV_M_MODE
# define RISCV_XMODE_OFFSET (RISCV_MACH_OFFSET)
# define RISCV_XRET mret
# define RISCV_MODE_PREFIX m
#elif RISCV_S_MODE
# define RISCV_XMODE_OFFSET (RISCV_SUPER_OFFSET)
# define RISCV_XRET sret
# define RISCV_MODE_PREFIX s
#else
# error Unrecognized RISC-V privilege level selected
#endif
@@ -36,14 +38,14 @@
#define RISCV_CSR_TIMEH (0xc81)
#define RISCV_CSR_INSRETH (0xc82)
#define RISCV_CSR_XSTATUS (0x000 | RISCV_CSR_XMODE_BITS)
#define RISCV_CSR_XIE (0x004 | RISCV_CSR_XMODE_BITS)
#define RISCV_CSR_XTVEC (0x005 | RISCV_CSR_XMODE_BITS)
#define RISCV_CSR_XSCRATCH (0x040 | RISCV_CSR_XMODE_BITS)
#define RISCV_CSR_XEPC (0x041 | RISCV_CSR_XMODE_BITS)
#define RISCV_CSR_XCAUSE (0x042 | RISCV_CSR_XMODE_BITS)
#define RISCV_CSR_XTVAL (0x043 | RISCV_CSR_XMODE_BITS)
#define RISCV_CSR_XIP (0x044 | RISCV_CSR_XMODE_BITS)
#define RISCV_CSR_XSTATUS __CONCAT(RISCV_MODE_PREFIX, status)
#define RISCV_CSR_XIE __CONCAT(RISCV_MODE_PREFIX, ie)
#define RISCV_CSR_XTVEC __CONCAT(RISCV_MODE_PREFIX, tvec)
#define RISCV_CSR_XSCRATCH __CONCAT(RISCV_MODE_PREFIX, scratch)
#define RISCV_CSR_XEPC __CONCAT(RISCV_MODE_PREFIX, epc)
#define RISCV_CSR_XCAUSE __CONCAT(RISCV_MODE_PREFIX, cause)
#define RISCV_CSR_XTVAL __CONCAT(RISCV_MODE_PREFIX, tval)
#define RISCV_CSR_XIP __CONCAT(RISCV_MODE_PREFIX, ip)
#if RISCV_M_MODE // Machine-mode only CSRs
#define RISCV_CSR_MCYCLE (0xb00)
@@ -55,7 +57,7 @@
#endif // RISCV_M_MODE
#if RISCV_S_MODE // Supervisor-mode only CSRs
#define RISCV_CSR_SATP (0x180)
#define RISCV_CSR_SATP satp
#endif
#define RISCV_CSR_XSTATUS_IE (1ul << (RISCV_XMODE_OFFSET + 0))

1
external/platform/pico/rp2_common/pico_platform/include/pico/platform.h vendored
View File

@@ -7,7 +7,6 @@
#ifndef _PICO_PLATFORM_H_
#define _PICO_PLATFORM_H_
#include <sys/cdefs.h>
#include "pico/types.h"
#include "hardware/platform_defs.h"

6
platform/rp20xx/include/sys/cdefs.h
View File

@@ -1,6 +0,0 @@
#pragma once
#ifndef __CONCAT
#define __CONCAT1(x,y) x ## y
#define __CONCAT(x,y) __CONCAT1(x,y)
#endif

3
top/include/lk/compiler.h
View File

@@ -11,6 +11,9 @@
#pragma once
#define __CONCAT1(x, y) x ## y
#define __CONCAT(x, y) __CONCAT1(x, y)
#ifndef __ASSEMBLY__
#if __GNUC__ || __clang__