[platform][rosco-m68k] Add port to the Rosco M68k board
Port to the really neat 68010 based board at https://rosco-m68k.com/ Port Features: -10Mhz 68010 -1MB ram -Dual UART + timer implemented as a 68c681 chip -timer running at 1Khz, UART A for console -interrupt driven RX support Some amount of extending of the 68k exceptinon code was needed to support the autovectored irqs that the 68681 uart uses. Added build system support for 68010.
This commit is contained in:
Travis Geiselbrecht
@@ -96,9 +96,10 @@ enum handler_return m68k_platform_irq(uint8_t m68k_irq) {
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LTRACEF("m68k irq vector %d\n", m68k_irq);
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// translate m68k irqs to pic numbers
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// incoming IRQs are from 0x19-0x1f (autovectored 1 - 7 on the cpu)
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int pic_num;
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if (likely(m68k_irq >= 1 && m68k_irq <= 6)) {
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pic_num = m68k_irq - 1;
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if (likely(m68k_irq >= 0x19 && m68k_irq <= 0x1f)) {
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pic_num = m68k_irq - 0x19;
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} else {
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panic("unhandled irq %d from cpu\n", m68k_irq);
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}
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@@ -3,6 +3,7 @@ LOCAL_DIR := $(GET_LOCAL_DIR)
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MODULE := $(LOCAL_DIR)
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ARCH := m68k
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M68K_CPU := 68040
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LK_HEAP_IMPLEMENTATION ?= dlmalloc
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MODULE_DEPS += lib/cbuf
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238
platform/rosco-m68k/duart.c
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238
platform/rosco-m68k/duart.c
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@@ -0,0 +1,238 @@
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/*
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* Copyright (c) 2021 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include "platform_p.h"
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#include <assert.h>
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#include <lk/err.h>
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#include <lk/debug.h>
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#include <lk/reg.h>
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#include <lk/trace.h>
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#include <lib/cbuf.h>
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#include <kernel/debug.h>
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#include <kernel/thread.h>
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#include <platform/interrupts.h>
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#include <platform/rosco-m68k.h>
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#include <platform/timer.h>
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#include <platform.h>
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#define LOCAL_TRACE 0
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// driver for a 68c681 acting as a dual uart and a system timer and a few gpios
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// ticks in units of ms
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static volatile uint32_t ticks;
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// periodic timer callback stuff
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static platform_timer_callback t_callback;
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static void *t_arg;
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static lk_time_t t_next_periodic_tick;
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static lk_time_t t_periodic_interval;
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// uart stuff
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#define RXBUF_SIZE 128
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static char uart_rx_buf_data[RXBUF_SIZE];
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static cbuf_t uart_rx_buf;
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static volatile uint8_t * const DUART_BASE = (void *)0xf00001;
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// registers, swizzled according to
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// https://github.com/rosco-m68k/rosco_m68k/blob/develop/code/shared/rosco_m68k_public.asm
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enum {
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DUART_REG_MR1A_RW = 0x00, // mode register, channel A
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DUART_REG_SRA_R = 0x01, // status register, channel A
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DUART_REG_CSRA_W = 0x01, // clock select register, channel A
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DUART_REG_MISR_R = 0x02, // masked interrupt status register
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DUART_REG_CRA_W = 0x02, // command register, channel A
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DUART_REG_RHRA_R = 0x03, // rx holding register, channel A
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DUART_REG_THRA_W = 0x03, // tx holding register, channel A
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DUART_REG_IPCR_R = 0x04, // input port config register
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DUART_REG_ACR_W = 0x04, // auxillary control register
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DUART_REG_ISR_R = 0x05, // interrupt status register
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DUART_REG_IMR_W = 0x05, // interrupt mask register
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DUART_REG_CTU_RW = 0x06, // counter timer, upper byte
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DUART_REG_CTL_RW = 0x07, // counter timer, lower byte
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DUART_REG_MR1B_RW = 0x08, // mode register, channel B
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DUART_REG_SRB_R = 0x09, // status register, channel B
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DUART_REG_CSRB_W = 0x09, // clock select register, channel B
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DUART_REG_CRB_W = 0x0a, // command register, channel B
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DUART_REG_RHRB_R = 0x0b, // rx holding register, channel B
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DUART_REG_THRB_W = 0x0b, // tx holding register, channel B
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DUART_REG_IVR_RW = 0x0c, // interrupt vector register
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DUART_REG_IP_R = 0x0d, // input port
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DUART_REG_OPCR_W = 0x0d, // output port configuration register
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DUART_REG_SCC_R = 0x0e, // start counter/timer command
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DUART_REG_STC_R = 0x0f, // stop counter/timer command
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DUART_REG_SOPBC_W = 0x0e, // set output port bits command
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DUART_REG_COPBC_W = 0x0f, // clear output port bits command
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};
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// save a copy of whatever IMR was set to before
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static uint8_t cached_imr;
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static void write_reg(uint reg, uint8_t val) {
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DUART_BASE[reg * 2] = val;
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}
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static uint8_t read_reg(uint reg) {
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return DUART_BASE[reg * 2];
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}
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void duart_early_init(void) {
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// clear all IRQs
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cached_imr = 0;
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write_reg(DUART_REG_IMR_W, cached_imr);
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// Set the IRQ vector to 0x45
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write_reg(DUART_REG_IVR_RW, 0x45);
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// TODO: set up UARTA again
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// for now assume it's already configured
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// set up a periodic counter at 1khz
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read_reg(DUART_REG_STC_R); // stop the counter
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// compute the counter
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uint16_t count = 3686400 / 2 / 1000;
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write_reg(DUART_REG_CTL_RW, count & 0xff);
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write_reg(DUART_REG_CTU_RW, (count >> 8) & 0xff);
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// set timer mode
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write_reg(DUART_REG_ACR_W, (0b110 << 4)); // timer mode, X1/CLK
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// start timer
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read_reg(DUART_REG_SCC_R); // start counter
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// unmask irq
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cached_imr = (1<<3); // counter #1 ready
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write_reg(DUART_REG_IMR_W, cached_imr);
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}
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void duart_init(void) {
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// finish uart init to get rx going
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cbuf_initialize_etc(&uart_rx_buf, RXBUF_SIZE, uart_rx_buf_data);
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// enable uart RX irq
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cached_imr |= (1<<1); // RXRDY/FFULLA
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write_reg(DUART_REG_IMR_W, cached_imr);
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}
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status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval) {
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LTRACEF("cb %p, arg %p, interval %u\n", callback, arg, interval);
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t_callback = callback;
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t_arg = arg;
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t_periodic_interval = interval;
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t_next_periodic_tick = current_time() + interval;
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return NO_ERROR;
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}
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enum handler_return duart_irq(void) {
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enum handler_return ret = INT_NO_RESCHEDULE;
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uint8_t isr = read_reg(DUART_REG_ISR_R);
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if (likely(isr & (1<<3))) { // counter #1 ready
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ticks++;
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// ack the timer hardware
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read_reg(DUART_REG_STC_R);
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// call back the registered timer
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if (likely(t_callback)) {
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lk_time_t now = current_time();
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if (unlikely(now >= t_next_periodic_tick)) {
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ret = t_callback(t_arg, now);
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t_next_periodic_tick += t_periodic_interval;
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}
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}
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}
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if (isr & (1<<1)) { // RXRDY/FFULLA
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uint8_t status = read_reg(DUART_REG_SRA_R);
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if (status & (1<<0)) { // RXRDY
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if (status & (0b111 << 5)) { // any of break, framing, or parity error
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// consume this byte
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__UNUSED volatile uint8_t hole = read_reg(DUART_REG_RHRA_R);
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} else {
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char c = read_reg(DUART_REG_RHRA_R);
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cbuf_write_char(&uart_rx_buf, c, false);
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ret = INT_RESCHEDULE;
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}
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}
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}
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return ret;
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}
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void platform_dputc(char c) {
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if (c == '\n') {
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platform_dputc('\r');
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}
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// spin while TXRDY is clear
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while ((read_reg(DUART_REG_SRA_R) & (1 << 2)) == 0) // TXRDY
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;
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write_reg(DUART_REG_THRA_W, c);
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}
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int platform_dgetc(char *c, bool wait) {
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return cbuf_read_char(&uart_rx_buf, c, wait);
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}
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int platform_pgetc(char *c, bool wait) {
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for (;;) {
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uint8_t status = read_reg(DUART_REG_SRA_R);
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if (status & (1<<0)) { // RXRDY
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if (status & (0b111 << 5)) { // any of break, framing, or parity error
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// consume this byte
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__UNUSED volatile uint8_t hole = read_reg(DUART_REG_RHRA_R);
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continue;
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}
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*c = read_reg(DUART_REG_RHRA_R);
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return 1;
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}
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if (wait) {
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continue;
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}
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break;
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} while (0);
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return 0;
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}
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lk_bigtime_t current_time_hires(void) {
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// TODO: look at the current countdown registers
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return ticks * 1000ULL;
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}
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lk_time_t current_time(void) {
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return ticks;
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}
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void target_set_debug_led(unsigned int led, bool on) {
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uint8_t bit = 0;
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switch (led) {
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case 0:
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bit = 5; // green LED
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break;
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case 1:
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bit = 3; // red LED
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break;
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}
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if (on) {
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write_reg(DUART_REG_SOPBC_W, (1<<bit));
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} else {
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write_reg(DUART_REG_COPBC_W, (1<<bit));
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}
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}
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71
platform/rosco-m68k/include/platform/rosco-m68k.h
Normal file
71
platform/rosco-m68k/include/platform/rosco-m68k.h
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@@ -0,0 +1,71 @@
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/*
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* Copyright (c) 2021 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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// TODO: add for rosco-m68k
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// Top level #defines for the 68k-virt machine in qemu 6.0
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//
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// From qemu/hw/m68k/virt.c
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/*
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* 6 goldfish-pic for CPU IRQ #1 to IRQ #6
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* CPU IRQ #1 -> PIC #1
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* IRQ #1 to IRQ #31 -> unused
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* IRQ #32 -> goldfish-tty
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* CPU IRQ #2 -> PIC #2
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* IRQ #1 to IRQ #32 -> virtio-mmio from 1 to 32
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* CPU IRQ #3 -> PIC #3
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* IRQ #1 to IRQ #32 -> virtio-mmio from 33 to 64
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* CPU IRQ #4 -> PIC #4
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* IRQ #1 to IRQ #32 -> virtio-mmio from 65 to 96
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* CPU IRQ #5 -> PIC #5
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* IRQ #1 to IRQ #32 -> virtio-mmio from 97 to 128
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* CPU IRQ #6 -> PIC #6
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* IRQ #1 -> goldfish-rtc
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* IRQ #2 to IRQ #32 -> unused
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* CPU IRQ #7 -> NMI
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*/
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#define NUM_PICS 6
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#define NUM_IRQS (NUM_PICS * 32) // PIC 1 - 6
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#define PIC_IRQ_TO_LINEAR(pic, irq) (((pic) - 1) * 32 + ((irq) - 1))
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#define GOLDFISH_TTY_IRQ PIC_IRQ_TO_LINEAR(1, 32) // PIC 1, irq 32
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#define GOLDFISH_RTC_IRQ PIC_IRQ_TO_LINEAR(6, 1) // PIC 6, irq 1
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#define PIC_IRQ_BASE(num) (8 + (num - 1) * 32)
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#define PIC_IRQ(num, irq) (PIC_IRQ_BASE(num) + irq - 1)
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//#define PIC_GPIO(pic_irq) (qdev_get_gpio_in(pic_dev[(pic_irq - 8) / 32], (pic_irq - 8) % 32))
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#define VIRT_GF_PIC_MMIO_BASE 0xff000000 /* MMIO: 0xff000000 - 0xff005fff */
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#define VIRT_GF_PIC_IRQ_BASE 1 /* IRQ: #1 -> #6 */
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#define VIRT_GF_PIC_NB 6
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/* 2 goldfish-rtc (and timer) */
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#define VIRT_GF_RTC_MMIO_BASE 0xff006000 /* MMIO: 0xff006000 - 0xff007fff */
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#define VIRT_GF_RTC_IRQ_BASE PIC_IRQ(6, 1) /* PIC: #6, IRQ: #1 */
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#define VIRT_GF_RTC_NB 2
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/* 1 goldfish-tty */
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#define VIRT_GF_TTY_MMIO_BASE 0xff008000 /* MMIO: 0xff008000 - 0xff008fff */
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#define VIRT_GF_TTY_IRQ_BASE PIC_IRQ(1, 32) /* PIC: #1, IRQ: #32 */
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/* 1 virt-ctrl */
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#define VIRT_CTRL_MMIO_BASE 0xff009000 /* MMIO: 0xff009000 - 0xff009fff */
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#define VIRT_CTRL_IRQ_BASE PIC_IRQ(1, 1) /* PIC: #1, IRQ: #1 */
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/*
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* virtio-mmio size is 0x200 bytes
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* we use 4 goldfish-pic to attach them,
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* we can attach 32 virtio devices / goldfish-pic
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* -> we can manage 32 * 4 = 128 virtio devices
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*/
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#define VIRT_VIRTIO_MMIO_BASE 0xff010000 /* MMIO: 0xff010000 - 0xff01ffff */
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#define VIRT_VIRTIO_IRQ_BASE PIC_IRQ(2, 1) /* PIC: 2, 3, 4, 5, IRQ: ALL */
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#define NUM_VIRT_VIRTIO 128
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70
platform/rosco-m68k/platform.c
Normal file
70
platform/rosco-m68k/platform.c
Normal file
@@ -0,0 +1,70 @@
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/*
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* Copyright (c) 2018 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#include <lk/err.h>
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#include <lk/reg.h>
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#include <lk/trace.h>
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#include <kernel/thread.h>
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#include <platform.h>
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#include <platform/interrupts.h>
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#include <platform/debug.h>
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#include <platform/timer.h>
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#include <platform/rosco-m68k.h>
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#include <sys/types.h>
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#if WITH_LIB_MINIP
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#include <lib/minip.h>
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#endif
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#include <kernel/novm.h>
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#if WITH_LIB_CONSOLE
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#include <lib/console.h>
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#endif
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#include "platform_p.h"
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#define LOCAL_TRACE 0
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extern uint8_t __bss_end;
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void platform_early_init(void) {
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duart_early_init();
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dprintf(INFO, "ROSCO-M68K: firmware structure at 0x400 - 0x41f:\n");
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hexdump((void *)0x400, 0x20);
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uint32_t cpu_info = *(uint32_t *)0x41c;
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printf("cpu family %u speed %u\n", cpu_info >> 29, cpu_info & 0x1fffffff);
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// TODO: probe memory
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// TODO: consider using firmware struct left around 0x400
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uint32_t membase = 0x0;
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uint32_t memsize = 0x100000; // 1MB
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dprintf(INFO, "ROSCO-M68K: memory base %#x size %#x\n", membase, memsize);
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novm_add_arena("mem", membase, memsize);
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// build a table of illegal instructions around 0 to try to catch bad branches
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volatile uint16_t *ptr = 0;
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for (int i = 0; i < 256; i++) {
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ptr[i] = 0x4afa; // undefined opcode
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}
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}
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void platform_init(void) {
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duart_init();
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}
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enum handler_return m68k_platform_irq(uint8_t irq) {
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LTRACEF("irq %u\n", irq);
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switch (irq) {
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case 0x45: // DUART irq
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return duart_irq();
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default:
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panic("unhandled platform irq %u\n", irq);
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}
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return INT_NO_RESCHEDULE;
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}
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14
platform/rosco-m68k/platform_p.h
Normal file
14
platform/rosco-m68k/platform_p.h
Normal file
@@ -0,0 +1,14 @@
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/*
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* Copyright (c) 2018 Travis Geiselbrecht
|
||||
*
|
||||
* Use of this source code is governed by a MIT-style
|
||||
* license that can be found in the LICENSE file or at
|
||||
* https://opensource.org/licenses/MIT
|
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*/
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#pragma once
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#include <stdbool.h>
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void duart_early_init(void);
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void duart_init(void);
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enum handler_return duart_irq(void);
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32
platform/rosco-m68k/rules.mk
Normal file
32
platform/rosco-m68k/rules.mk
Normal file
@@ -0,0 +1,32 @@
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LOCAL_DIR := $(GET_LOCAL_DIR)
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MODULE := $(LOCAL_DIR)
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ARCH := m68k
|
||||
M68K_CPU := 68010
|
||||
LK_HEAP_IMPLEMENTATION ?= dlmalloc
|
||||
|
||||
MODULE_DEPS += lib/cbuf
|
||||
|
||||
#MODULE_SRCS += $(LOCAL_DIR)/goldfish_rtc.c
|
||||
#MODULE_SRCS += $(LOCAL_DIR)/goldfish_tty.c
|
||||
#MODULE_SRCS += $(LOCAL_DIR)/pic.c
|
||||
MODULE_SRCS += $(LOCAL_DIR)/duart.c
|
||||
MODULE_SRCS += $(LOCAL_DIR)/platform.c
|
||||
|
||||
MEMBASE ?= 0x00002000 # 8k. Just off the end of firmware reserved areas
|
||||
MEMSIZE ?= 0x00100000 # 1MB
|
||||
|
||||
# relocate ourself from the load address (0x40000)
|
||||
GLOBAL_DEFINES += ARCH_DO_RELOCATION=1
|
||||
|
||||
# we can revert to a poll based uart spin routine
|
||||
GLOBAL_DEFINES += PLATFORM_SUPPORTS_PANIC_SHELL=1
|
||||
|
||||
# we will find the memory size by probing it
|
||||
GLOBAL_DEFINES += NOVM_DEFAULT_ARENA=0
|
||||
|
||||
# we will find the memory size by probing it
|
||||
GLOBAL_DEFINES += TARGET_HAS_DEBUG_LED=1
|
||||
|
||||
include make/module.mk
|
||||
Reference in New Issue
Block a user