[platform/target][warnings] fix -Wmissing-declarations warnings in platform/ and target/

Mostly driver code in various platforms. There are still some warnings
in this part of the tree in lesser-used platforms.

platform/zynq/gem.c

@@ -130,7 +130,7 @@ static int free_completed_pbuf_frames(void) {
     return ret;
 }
 
-void queue_pkts_in_tx_tbl(void) {
+static void queue_pkts_in_tx_tbl(void) {
     pktbuf_t *p;
     unsigned int cur_pos;
 
@@ -194,7 +194,7 @@ err:
 }
 
 
-enum handler_return gem_int_handler(void *arg) {
+static enum handler_return gem_int_handler(void *arg) {
     uint32_t intr_status;
     bool resched = false;
 
@@ -336,7 +336,7 @@ static void gem_cfg_ints(void) {
                         INTR_RX_USED_READ | INTR_TX_CORRUPT | INTR_TX_USED_READ | INTR_RX_OVERRUN;
 }
 
-int gem_rx_thread(void *arg) {
+static int gem_rx_thread(void *arg) {
     pktbuf_t *p;
     int bp = 0;
 
@@ -386,7 +386,7 @@ int gem_rx_thread(void *arg) {
 }
 
 
-int gem_stat_thread(void *arg) {
+static int gem_stat_thread(void *arg) {
     volatile bool *run = ((bool *)arg);
     static uint32_t frames_rx = 0, frames_tx = 0;
 
@@ -401,7 +401,7 @@ int gem_stat_thread(void *arg) {
     return 0;
 }
 
-void gem_deinit(uintptr_t base) {
+static void gem_deinit(uintptr_t base) {
     /* reset the gem peripheral */
     uint32_t rst_mask;
     if (base == GEM0_BASE) {

platform/zynq/platform.c

@@ -35,6 +35,7 @@ STATIC_ASSERT(SDRAM_SIZE != 0);
 static uint32_t saved_reboot_status;
 
 /* target can specify this as the initial jam table to set up the soc */
+void ps7_init(void);
 __WEAK void ps7_init(void) { }
 
 /* These should be defined in the target somewhere */
@@ -60,7 +61,7 @@ static inline int reg_poll(uint32_t addr,uint32_t mask) {
  * before doing a reset to switch to the new values. Then bypass is removed to switch back to using
  * the PLL once its locked.
  */
-int zynq_pll_init(void) {
+static int zynq_pll_init(void) {
     const zynq_pll_cfg_tree_t *cfg = &zynq_pll_cfg;
 
     SLCR_REG(ARM_PLL_CFG)  = PLL_CFG_LOCK_CNT(cfg->arm.lock_cnt) | PLL_CFG_PLL_CP(cfg->arm.cp) |
@@ -105,7 +106,7 @@ int zynq_pll_init(void) {
     return 0;
 }
 
-int zynq_mio_init(void) {
+static int zynq_mio_init(void) {
 
     /* This DDRIOB configuration applies to both zybo and uzed, but it's possible
      * it may not work for all boards in the future. Just something to keep in mind
@@ -124,7 +125,7 @@ int zynq_mio_init(void) {
     return 0;
 }
 
-void zynq_clk_init(void) {
+static void zynq_clk_init(void) {
     SLCR_REG(DCI_CLK_CTRL)   = zynq_clk_cfg.dci_clk;
     SLCR_REG(GEM0_CLK_CTRL)  = zynq_clk_cfg.gem0_clk;
     SLCR_REG(GEM0_RCLK_CTRL) = zynq_clk_cfg.gem0_rclk;
@@ -149,7 +150,7 @@ void zynq_clk_init(void) {
 }
 
 #if ZYNQ_SDRAM_INIT
-void zynq_ddr_init(void) {
+static void zynq_ddr_init(void) {
     SLCR_REG(DDRIOB_ADDR0) = zynq_ddriob_cfg.addr0;
     SLCR_REG(DDRIOB_ADDR1) = zynq_ddriob_cfg.addr1;
     SLCR_REG(DDRIOB_DATA0) = zynq_ddriob_cfg.data0;
@@ -446,6 +447,7 @@ void platform_quiesce(void) {
  * having the BOOT_MODE pins set to JTAG should cause us to hang out in
  * whatever binary is loaded at the time.
  */
+bool platform_abort_autoboot(void);
 bool platform_abort_autoboot(void) {
     /* test BOOT_MODE pins to see if we want to skip the autoboot stuff */
     uint32_t boot_mode = zynq_get_boot_mode();

platform/zynq/spiflash.c

@@ -21,6 +21,7 @@
 #include <lib/bio.h>
 #include <lk/console_cmd.h>
 #include <dev/qspi.h>
+#include <dev/spiflash.h>
 #include <kernel/thread.h>
 
 #include <platform/zynq.h>
@@ -409,7 +410,7 @@ static int spiflash_ioctl(struct bdev *bdev, int request, void *argp) {
 }
 
 // debug tests
-int cmd_spiflash(int argc, const console_cmd_args *argv) {
+static int cmd_spiflash(int argc, const console_cmd_args *argv) {
     if (argc < 2) {
 notenoughargs:
         printf("not enough arguments\n");

platform/zynq/uart.c

@@ -11,6 +11,7 @@
 #include <assert.h>
 #include <lib/cbuf.h>
 #include <kernel/thread.h>
+#include <dev/uart.h>
 #include <platform/interrupts.h>
 #include <platform/debug.h>
 #include <platform/zynq.h>