[platform/target][warnings] fix -Wmissing-declarations warnings in platform/ and target/

Mostly driver code in various platforms. There are still some warnings
in this part of the tree in lesser-used platforms.

platform/alterasoc/uart.c

@@ -10,6 +10,7 @@
 #include <stdio.h>
 #include <lk/trace.h>
 #include <lib/cbuf.h>
+#include <dev/uart.h>
 #include <kernel/thread.h>
 #include <kernel/spinlock.h>
 #include <platform/interrupts.h>

platform/amlogic-s912d/uart.c

@@ -88,7 +88,7 @@ int uart_getc(int port, bool wait) {
     }
 }
 
-enum handler_return uart_irq_handler(void *arg) {
+static enum handler_return uart_irq_handler(void *arg) {
     while ( (UARTREG(uart_base, S912D_UART_STATUS) & S912D_UART_STATUS_RXCOUNT_MASK) > 0 ) {
         if (cbuf_space_avail(&uart_rx_buf) == 0) {
             break;

platform/include/platform/timer.h

@@ -26,10 +26,8 @@ typedef enum handler_return (*platform_timer_callback)(void *arg, lk_time_t now)
 status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval);
 
 /* If the platform implements a full dynamic (can be set to arbitary points in the future) timer */
-#if PLATFORM_HAS_DYNAMIC_TIMER
 status_t platform_set_oneshot_timer (platform_timer_callback callback, void *arg, lk_time_t interval);
 void     platform_stop_timer(void);
-#endif
 
 __END_CDECLS
 

platform/microblaze/intc.c

@@ -70,6 +70,7 @@ status_t unmask_interrupt(unsigned int vector) {
     return NO_ERROR;
 }
 
+enum handler_return platform_irq_handler(void);
 enum handler_return platform_irq_handler(void) {
     enum handler_return ret = INT_NO_RESCHEDULE;
 

platform/microblaze/platform.c

@@ -14,8 +14,7 @@
 #include <sys/types.h>
 #include <target/microblaze-config.h>
 
-void uartlite_putc(char c);
-int uartlite_getc(bool wait);
+#include "uartlite.h"
 
 void platform_dputc(char c) {
     if (c == '\n')

platform/microblaze/timer.c

@@ -68,7 +68,7 @@ lk_time_t current_time(void) {
     return (lk_time_t)ticks * 10;
 }
 
-enum handler_return timer_irq(void *arg) {
+static enum handler_return timer_irq(void *arg) {
     LTRACE;
 
     TIMER_REG(R_TCSR) |= TCSR_TINT;

platform/microblaze/uartlite.c

@@ -15,6 +15,8 @@
 #include <sys/types.h>
 #include <target/microblaze-config.h>
 
+#include "uartlite.h"
+
 #define LOCAL_TRACE 0
 
 #define R_RX            0
@@ -64,7 +66,7 @@ int uartlite_getc(bool wait) {
     return -1;
 }
 
-enum handler_return uartlite_irq(void *arg) {
+static enum handler_return uartlite_irq(void *arg) {
     bool resched = false;
 
     /* while receive fifo not empty, read a char */

platform/microblaze/uartlite.h

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2015 Travis Geiselbrecht
+ *
+ * Use of this source code is governed by a MIT-style
+ * license that can be found in the LICENSE file or at
+ * https://opensource.org/licenses/MIT
+ */
+#include <stdbool.h>
+
+void uartlite_putc(char c);
+int uartlite_getc(bool wait);
+

platform/pc/debug.c

@@ -11,12 +11,15 @@
 #include <kernel/thread.h>
 #include <arch/x86.h>
 #include <lib/cbuf.h>
+#include <platform.h>
 #include <platform/interrupts.h>
 #include <platform/pc.h>
 #include <platform/console.h>
 #include <platform/keyboard.h>
 #include <platform/debug.h>
 
+#include "platform_p.h"
+
 #ifndef DEBUG_BAUD_RATE
 #define DEBUG_BAUD_RATE 115200
 #endif
@@ -92,7 +95,8 @@ int platform_dgetc(char *c, bool wait) {
     return cbuf_read_char(&console_input_buf, c, wait);
 }
 
-void platform_halt(void) {
+void platform_halt(platform_halt_action suggested_action,
+                   platform_halt_reason reason) {
     for (;;) {
         x86_cli();
         x86_hlt();

platform/pc/interrupts.c

@@ -21,13 +21,6 @@
 
 static spin_lock_t lock;
 
-void x86_gpf_handler(x86_iframe_t *frame);
-void x86_invop_handler(x86_iframe_t *frame);
-void x86_unhandled_exception(x86_iframe_t *frame);
-#ifdef ARCH_X86_64
-void x86_pfe_handler(x86_iframe_t *frame);
-#endif
-
 #define PIC1 0x20
 #define PIC2 0xA0
 
@@ -126,7 +119,7 @@ static void enable(unsigned int vector, bool enable) {
     }
 }
 
-void issueEOI(unsigned int vector) {
+static void issueEOI(unsigned int vector) {
     if (vector >= PIC1_BASE && vector <= PIC1_BASE + 7) {
         outp(PIC1, 0x20);
     } else if (vector >= PIC2_BASE && vector <= PIC2_BASE + 7) {
@@ -157,7 +150,7 @@ status_t mask_interrupt(unsigned int vector) {
 }
 
 
-void platform_mask_irqs(void) {
+static void platform_mask_irqs(void) {
     irqMask[0] = inp(PIC1 + 1);
     irqMask[1] = inp(PIC2 + 1);
 
@@ -184,6 +177,7 @@ status_t unmask_interrupt(unsigned int vector) {
     return NO_ERROR;
 }
 
+enum handler_return platform_irq(x86_iframe_t *frame);
 enum handler_return platform_irq(x86_iframe_t *frame) {
     // get the current vector
     unsigned int vector = frame->vector;

platform/pc/platform.c

@@ -151,7 +151,7 @@ static pmm_arena_t mem_arena = {
 /* set up the size of the physical memory map based on the end of memory we detected in
  * platform_init_multiboot_info()
  */
-void mem_arena_init(void) {
+static void mem_arena_init(void) {
     uintptr_t mem_base = (uintptr_t)MEMBASE;
     uintptr_t mem_size = mem_top;
 
@@ -160,7 +160,7 @@ void mem_arena_init(void) {
 }
 #endif
 
-void platform_init_multiboot_info(void) {
+static void platform_init_multiboot_info(void) {
     LTRACEF("_multiboot_info %p\n", _multiboot_info);
     if (_multiboot_info) {
         /* bump the multiboot pointer up to the kernel mapping */

platform/pc/timer.c

@@ -141,12 +141,10 @@ void platform_init_timer(void) {
     unmask_interrupt(INT_PIT);
 }
 
-void platform_halt_timers(void) {
+static void platform_halt_timers(void) {
     mask_interrupt(INT_PIT);
 }
 
-
-
 status_t platform_set_oneshot_timer(platform_timer_callback callback,
                                     void *arg, lk_time_t interval) {
 

platform/qemu-mips/debug.c

@@ -9,9 +9,11 @@
 #include <stdarg.h>
 #include <lk/reg.h>
 #include <lk/trace.h>
+#include <lk/err.h>
 #include <stdio.h>
 #include <kernel/thread.h>
 #include <lib/cbuf.h>
+#include <dev/uart.h>
 #include <platform/interrupts.h>
 #include <platform/qemu-mips.h>
 
@@ -33,7 +35,7 @@ static enum handler_return uart_irq_handler(void *arg) {
     return resched ? INT_RESCHEDULE : INT_NO_RESCHEDULE;
 }
 
-void platform_init_uart(void) {
+void uart_init_early(void) {
     /* configure the uart */
     int divisor = 115200 / uart_baud_rate;
 
@@ -55,14 +57,20 @@ void uart_init(void) {
     isa_write_8(uart_io_port + 1, 0x1); // enable receive data available interrupt
 }
 
-void uart_putc(char c) {
+int uart_putc(int port, char c) {
     while ((isa_read_8(uart_io_port + 5) & (1<<6)) == 0)
         ;
     isa_write_8(uart_io_port + 0, c);
+    return 0;
 }
 
-int uart_getc(char *c, bool wait) {
-    return cbuf_read_char(&uart_rx_buf, c, wait);
+int uart_getc(int port, bool wait) {
+    char c;
+    if (cbuf_read_char(&uart_rx_buf, &c, wait) == 1) {
+        return c;
+    } else {
+        return -1;
+    }
 }
 
 void platform_dputc(char c) {
@@ -71,7 +79,7 @@ void platform_dputc(char c) {
 #if WITH_CGA_CONSOLE
     cputc(c);
 #else
-    uart_putc(c);
+    uart_putc(0, c);
 #endif
 }
 
@@ -81,7 +89,10 @@ int platform_dgetc(char *c, bool wait) {
     //if (ret < 0)
     //  arch_idle();
 #else
-    int ret = uart_getc(c, wait);
+    int ret = uart_getc(0, wait);
+    if (ret >= 0) {
+        *c = ret;
+    }
 #endif
 
     return ret;

platform/qemu-mips/platform.c

@@ -14,6 +14,7 @@
 #include <platform/timer.h>
 #include <platform/qemu-mips.h>
 #include <arch/mips.h>
+#include <dev/uart.h>
 
 extern void platform_init_interrupts(void);
 extern void platform_init_uart(void);
@@ -21,7 +22,7 @@ extern void uart_init(void);
 
 void platform_early_init(void) {
     platform_init_interrupts();
-    platform_init_uart();
+    uart_init_early();
 
     mips_init_timer(100000000);
     mips_enable_irq(2);

platform/qemu-virt-arm/uart.c

@@ -9,6 +9,7 @@
 #include <stdio.h>
 #include <lk/trace.h>
 #include <lib/cbuf.h>
+#include <dev/uart.h>
 #include <kernel/thread.h>
 #include <platform/interrupts.h>
 #include <platform/debug.h>
@@ -151,7 +152,7 @@ int uart_pputc(int port, char c) {
     return 1;
 }
 
-int uart_pgetc(int port, bool wait) {
+int uart_pgetc(int port) {
     uintptr_t base = uart_to_ptr(port);
 
     if ((UARTREG(base, UART_TFR) & (1<<4)) == 0) {

platform/qemu-virt-riscv/uart.c

@@ -57,13 +57,13 @@ void uart_init(void) {
     unmask_interrupt(IRQ_UART0);
 }
 
-void uart_putc(char c) {
+static void uart_putc(char c) {
     while ((uart_read_8(5) & (1<<6)) == 0)
         ;
     uart_write_8(0, c);
 }
 
-int uart_getc(char *c, bool wait) {
+static int uart_getc(char *c, bool wait) {
     return cbuf_read_char(&uart_rx_buf, c, wait);
 }
 

platform/sifive/gpio.c

@@ -16,6 +16,8 @@
 #include <sys/types.h>
 #include <dev/gpio.h>
 
+#include "platform_p.h"
+
 static volatile unsigned int *const gpio_base = (unsigned int *)GPIO_BASE;
 
 #define GPIO_REG_VALUE      0

platform/stm32f1xx/debug.c

@@ -17,6 +17,7 @@
 #include <stm32f10x_rcc.h>
 #include <stm32f10x_usart.h>
 #include <arch/arm/cm.h>
+#include <platform/stm32.h>
 
 void stm32_debug_early_init(void) {
     uart_init_early();

platform/stm32f1xx/flash_nor.c

@@ -11,6 +11,7 @@
 #include <sys/types.h>
 #include <kernel/thread.h>
 #include <platform.h>
+#include <platform/stm32.h>
 #include <dev/flash_nor.h>
 #include <stm32f10x_rcc.h>
 #include <stm32f10x_flash.h>

platform/stm32f1xx/timer.c

@@ -12,6 +12,7 @@
 #include <kernel/thread.h>
 #include <platform.h>
 #include <platform/timer.h>
+#include <platform/stm32.h>
 #include <stm32f10x_rcc.h>
 #include <stm32f10x_tim.h>
 #include <misc.h>
@@ -22,6 +23,9 @@
 #define TIME_BASE_COUNT 0xffff
 #define TICK_RATE 1000000
 
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-declarations"
+
 static void stm32_tim_irq(uint num) {
     TRACEF("tim irq %d\n", num);
     PANIC_UNIMPLEMENTED;
@@ -52,6 +56,8 @@ void stm32_TIM2_IRQ(void) {
     stm32_tim_irq(2);
 }
 
+#pragma GCC diagnostic pop
+
 void stm32_timer_early_init(void) {
 }
 

platform/stm32f1xx/uart.c

@@ -107,7 +107,7 @@ void uart_init(void) {
 #endif
 }
 
-void uart_rx_irq(USART_TypeDef *usart, cbuf_t *rxbuf) {
+static void uart_rx_irq(USART_TypeDef *usart, cbuf_t *rxbuf) {
     arm_cm_irq_entry();
 
     bool resched = false;
@@ -128,18 +128,21 @@ void uart_rx_irq(USART_TypeDef *usart, cbuf_t *rxbuf) {
 }
 
 #ifdef ENABLE_UART1
+void stm32_USART1_IRQ(void);
 void stm32_USART1_IRQ(void) {
     uart_rx_irq(USART1, &uart1_rx_buf);
 }
 #endif
 
 #ifdef ENABLE_UART2
+void stm32_USART2_IRQ(void);
 void stm32_USART2_IRQ(void) {
     uart_rx_irq(USART2, &uart2_rx_buf);
 }
 #endif
 
 #ifdef ENABLE_UART3
+void stm32_USART3_IRQ(void);
 void stm32_USART3_IRQ(void) {
     uart_rx_irq(USART3, &uart3_rx_buf);
 }

platform/stm32f1xx/vectab.c

@@ -14,6 +14,7 @@
 #include <lib/cbuf.h>
 
 /* un-overridden irq handler */
+void stm32_dummy_irq(void);
 void stm32_dummy_irq(void) {
     arm_cm_irq_entry();
 

platform/stm32f4xx/debug.c

@@ -14,6 +14,7 @@
 #include <arch/ops.h>
 #include <dev/uart.h>
 #include <target/debugconfig.h>
+#include <platform/stm32.h>
 #include <stm32f4xx_rcc.h>
 #include <stm32f4xx_usart.h>
 #include <arch/arm/cm.h>

platform/stm32f4xx/timer.c

@@ -12,6 +12,7 @@
 #include <kernel/thread.h>
 #include <platform.h>
 #include <platform/timer.h>
+#include <platform/stm32.h>
 #include <stm32f4xx_rcc.h>
 #include <stm32f4xx_tim.h>
 #include <misc.h>
@@ -19,6 +20,8 @@
 
 #define LOCAL_TRACE 0
 
+#pragma GCC diagnostic ignored "-Wmissing-declarations"
+
 static void stm32_tim_irq(uint num) {
     TRACEF("tim irq %d\n", num);
     PANIC_UNIMPLEMENTED;

platform/stm32f4xx/uart.c

@@ -129,7 +129,7 @@ void uart_init(void) {
 #endif
 }
 
-void uart_rx_irq(USART_TypeDef *usart, cbuf_t *rxbuf) {
+static void uart_rx_irq(USART_TypeDef *usart, cbuf_t *rxbuf) {
     arm_cm_irq_entry();
 
     bool resched = false;

platform/stm32f4xx/vectab.c

@@ -14,7 +14,7 @@
 #include <lib/cbuf.h>
 
 /* un-overridden irq handler */
-void stm32_dummy_irq(void) {
+static void stm32_dummy_irq(void) {
     arm_cm_irq_entry();
 
     panic("unhandled irq\n");

platform/zynq/gem.c

@@ -130,7 +130,7 @@ static int free_completed_pbuf_frames(void) {
     return ret;
 }
 
-void queue_pkts_in_tx_tbl(void) {
+static void queue_pkts_in_tx_tbl(void) {
     pktbuf_t *p;
     unsigned int cur_pos;
 
@@ -194,7 +194,7 @@ err:
 }
 
 
-enum handler_return gem_int_handler(void *arg) {
+static enum handler_return gem_int_handler(void *arg) {
     uint32_t intr_status;
     bool resched = false;
 
@@ -336,7 +336,7 @@ static void gem_cfg_ints(void) {
                         INTR_RX_USED_READ | INTR_TX_CORRUPT | INTR_TX_USED_READ | INTR_RX_OVERRUN;
 }
 
-int gem_rx_thread(void *arg) {
+static int gem_rx_thread(void *arg) {
     pktbuf_t *p;
     int bp = 0;
 
@@ -386,7 +386,7 @@ int gem_rx_thread(void *arg) {
 }
 
 
-int gem_stat_thread(void *arg) {
+static int gem_stat_thread(void *arg) {
     volatile bool *run = ((bool *)arg);
     static uint32_t frames_rx = 0, frames_tx = 0;
 
@@ -401,7 +401,7 @@ int gem_stat_thread(void *arg) {
     return 0;
 }
 
-void gem_deinit(uintptr_t base) {
+static void gem_deinit(uintptr_t base) {
     /* reset the gem peripheral */
     uint32_t rst_mask;
     if (base == GEM0_BASE) {

platform/zynq/platform.c

@@ -35,6 +35,7 @@ STATIC_ASSERT(SDRAM_SIZE != 0);
 static uint32_t saved_reboot_status;
 
 /* target can specify this as the initial jam table to set up the soc */
+void ps7_init(void);
 __WEAK void ps7_init(void) { }
 
 /* These should be defined in the target somewhere */
@@ -60,7 +61,7 @@ static inline int reg_poll(uint32_t addr,uint32_t mask) {
  * before doing a reset to switch to the new values. Then bypass is removed to switch back to using
  * the PLL once its locked.
  */
-int zynq_pll_init(void) {
+static int zynq_pll_init(void) {
     const zynq_pll_cfg_tree_t *cfg = &zynq_pll_cfg;
 
     SLCR_REG(ARM_PLL_CFG)  = PLL_CFG_LOCK_CNT(cfg->arm.lock_cnt) | PLL_CFG_PLL_CP(cfg->arm.cp) |
@@ -105,7 +106,7 @@ int zynq_pll_init(void) {
     return 0;
 }
 
-int zynq_mio_init(void) {
+static int zynq_mio_init(void) {
 
     /* This DDRIOB configuration applies to both zybo and uzed, but it's possible
      * it may not work for all boards in the future. Just something to keep in mind
@@ -124,7 +125,7 @@ int zynq_mio_init(void) {
     return 0;
 }
 
-void zynq_clk_init(void) {
+static void zynq_clk_init(void) {
     SLCR_REG(DCI_CLK_CTRL)   = zynq_clk_cfg.dci_clk;
     SLCR_REG(GEM0_CLK_CTRL)  = zynq_clk_cfg.gem0_clk;
     SLCR_REG(GEM0_RCLK_CTRL) = zynq_clk_cfg.gem0_rclk;
@@ -149,7 +150,7 @@ void zynq_clk_init(void) {
 }
 
 #if ZYNQ_SDRAM_INIT
-void zynq_ddr_init(void) {
+static void zynq_ddr_init(void) {
     SLCR_REG(DDRIOB_ADDR0) = zynq_ddriob_cfg.addr0;
     SLCR_REG(DDRIOB_ADDR1) = zynq_ddriob_cfg.addr1;
     SLCR_REG(DDRIOB_DATA0) = zynq_ddriob_cfg.data0;
@@ -446,6 +447,7 @@ void platform_quiesce(void) {
  * having the BOOT_MODE pins set to JTAG should cause us to hang out in
  * whatever binary is loaded at the time.
  */
+bool platform_abort_autoboot(void);
 bool platform_abort_autoboot(void) {
     /* test BOOT_MODE pins to see if we want to skip the autoboot stuff */
     uint32_t boot_mode = zynq_get_boot_mode();

platform/zynq/spiflash.c

@@ -21,6 +21,7 @@
 #include <lib/bio.h>
 #include <lk/console_cmd.h>
 #include <dev/qspi.h>
+#include <dev/spiflash.h>
 #include <kernel/thread.h>
 
 #include <platform/zynq.h>
@@ -409,7 +410,7 @@ static int spiflash_ioctl(struct bdev *bdev, int request, void *argp) {
 }
 
 // debug tests
-int cmd_spiflash(int argc, const console_cmd_args *argv) {
+static int cmd_spiflash(int argc, const console_cmd_args *argv) {
     if (argc < 2) {
 notenoughargs:
         printf("not enough arguments\n");

platform/zynq/uart.c

@@ -11,6 +11,7 @@
 #include <assert.h>
 #include <lib/cbuf.h>
 #include <kernel/thread.h>
+#include <dev/uart.h>
 #include <platform/interrupts.h>
 #include <platform/debug.h>
 #include <platform/zynq.h>

target/init.c

@@ -21,9 +21,6 @@ __WEAK void target_early_init(void) {
 __WEAK void target_init(void) {
 }
 
-__WEAK void target_set_led(unsigned int led, bool on) {
-}
-
 __WEAK void target_quiesce(void) {
 }
 

target/pc-x86/config.c

@@ -13,6 +13,7 @@
 #include <platform/ide.h>
 #include <platform/pcnet.h>
 #include <platform.h>
+#include <target.h>
 #include <malloc.h>
 #include <string.h>
 #include <lk/debug.h>

target/uzed/target.c

@@ -12,6 +12,7 @@
 #include <kernel/vm.h>
 #include <platform/zynq.h>
 #include <platform/gem.h>
+#include <target.h>
 
 zynq_pll_cfg_tree_t zynq_pll_cfg = {
     .arm = {

target/zybo/target.c

@@ -15,6 +15,7 @@
 #include <platform/gem.h>
 #include <platform/gpio.h>
 #include <platform/interrupts.h>
+#include <target.h>
 #include <target/gpioconfig.h>
 
 zynq_pll_cfg_tree_t zynq_pll_cfg = {