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[platform][stellaris] begin of a gpio api

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This commit is contained in:
Travis Geiselbrecht
2013-03-18 01:41:39 -07:00
parent 764fa1681c
commit 3dffd4ea6b
6 changed files with 209 additions and 34 deletions
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20
platform/stellaris/debug.c
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@@ -73,14 +73,17 @@ void stellaris_uart_irq(void)
void stellaris_debug_early_init(void)
{
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
// Set GPIO A0 and A1 as UART pins.
//
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
/* we only support UART0 right now */
STATIC_ASSERT(DEBUG_UART == UART0_BASE);
if (DEBUG_UART == UART0_BASE) {
/* Set GPIO A0 and A1 as UART pins. */
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
GPIOPinTypeUART(GPIO_PORTA_AHB_BASE, GPIO_PIN_0 | GPIO_PIN_1);
}
UARTConfigSetExpClk(DEBUG_UART, SysCtlClockGet(), 115200, UART_CONFIG_WLEN_8|UART_CONFIG_STOP_ONE|UART_CONFIG_PAR_NONE);
@@ -91,10 +94,7 @@ void stellaris_debug_init(void)
{
cbuf_initialize(&debug_rx_buf, 16);
//
// Enable the UART interrupt.
//
//ROM_IntEnable(INT_UART0);
/* Enable the UART interrupt. */
UARTIntEnable(DEBUG_UART, UART_INT_RX | UART_INT_RT);
NVIC_EnableIRQ(INT_UART0 - 16);

141
platform/stellaris/gpio.c Normal file
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@@ -0,0 +1,141 @@
/*
* Copyright (c) 2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <debug.h>
#include <assert.h>
#include <dev/gpio.h>
#include <platform/gpio.h>
#include "ti_driverlib.h"
static void *port_to_pointer(unsigned int port)
{
switch (port) {
default:
case GPIO_PORT_A:
return (void *)GPIO_PORTA_AHB_BASE;
case GPIO_PORT_B:
return (void *)GPIO_PORTB_AHB_BASE;
case GPIO_PORT_C:
return (void *)GPIO_PORTC_AHB_BASE;
case GPIO_PORT_D:
return (void *)GPIO_PORTD_AHB_BASE;
case GPIO_PORT_E:
return (void *)GPIO_PORTE_AHB_BASE;
case GPIO_PORT_F:
return (void *)GPIO_PORTF_AHB_BASE;
case GPIO_PORT_G:
return (void *)GPIO_PORTG_AHB_BASE;
case GPIO_PORT_H:
return (void *)GPIO_PORTH_AHB_BASE;
case GPIO_PORT_J:
return (void *)GPIO_PORTJ_BASE;
case GPIO_PORT_K:
return (void *)GPIO_PORTK_BASE;
case GPIO_PORT_L:
return (void *)GPIO_PORTL_BASE;
case GPIO_PORT_M:
return (void *)GPIO_PORTM_BASE;
case GPIO_PORT_N:
return (void *)GPIO_PORTN_BASE;
case GPIO_PORT_P:
return (void *)GPIO_PORTP_BASE;
case GPIO_PORT_Q:
return (void *)GPIO_PORTQ_BASE;
}
}
void stellaris_gpio_early_init(void)
{
SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOA);
SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOB);
SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOC);
SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOD);
SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOE);
SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOF);
SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOG);
SysCtlGPIOAHBEnable(SYSCTL_PERIPH_GPIOH);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
}
void stellaris_gpio_init(void)
{
}
#if 0
int gpio_config(unsigned nr, unsigned flags)
{
uint port = GPIO_PORT(nr);
uint pin = GPIO_PIN(nr);
enable_port(port);
GPIO_InitTypeDef init;
init.GPIO_Speed = GPIO_Speed_50MHz;
init.GPIO_Pin = (1 << pin);
if (flags & GPIO_STM32_AF) {
if (flags & GPIO_STM32_OD)
init.GPIO_Mode = GPIO_Mode_Out_OD;
else
init.GPIO_Mode = GPIO_Mode_AF_PP;
} else if (flags & GPIO_OUTPUT) {
if (flags & GPIO_STM32_OD)
init.GPIO_Mode = GPIO_Mode_Out_OD;
else
init.GPIO_Mode = GPIO_Mode_Out_PP;
} else { // GPIO_INPUT
if (flags & GPIO_PULLUP) {
init.GPIO_Mode = GPIO_Mode_IPU;
} else if (flags & GPIO_PULLDOWN) {
init.GPIO_Mode = GPIO_Mode_IPD;
} else {
init.GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
}
GPIO_Init(port_to_pointer(port), &init);
return 0;
}
#endif
void gpio_set(unsigned nr, unsigned on)
{
GPIOPinWrite((unsigned int)port_to_pointer(GPIO_PORT(nr)), 1 << GPIO_PIN(nr), on ? (1 << GPIO_PIN(nr)) : 0);
}
int gpio_get(unsigned nr)
{
return GPIOPinRead((unsigned int)port_to_pointer(GPIO_PORT(nr)), 1 << GPIO_PIN(nr));
}

37
platform/stellaris/include/platform/gpio.h Normal file
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@@ -0,0 +1,37 @@
#ifndef __PLATFORM_STELLARIS_GPIO_H
#define __PLATFORM_STELLARIS_GPIO_H
/* helper defines for Stellaris platforms */
/* flag to gpio_configure */
#define GPIO_STELLARIS_OD (0x1 << 12)
#define GPIO_STELLARIS_AF_ENABLE (0x2 << 12)
#define GPIO_STELLARIS_AF(x) (((x) & 0xf) << 8)
/* gpio port/pin is packed into a single unsigned int in 20x:4alternatefunc:4port:4pin format */
#define GPIO(port, pin) ((unsigned int)(((port) << 4) | (pin)))
#define GPIO_PORT(gpio) (((gpio) >> 4) & 0xf)
#define GPIO_PIN(gpio) ((gpio) & 0xf)
#define GPIO_PORT_A 0
#define GPIO_PORT_B 1
#define GPIO_PORT_C 2
#define GPIO_PORT_D 3
#define GPIO_PORT_E 4
#define GPIO_PORT_F 5
#define GPIO_PORT_G 6
#define GPIO_PORT_H 7
/* discontinuity */
#define GPIO_PORT_J 8
#define GPIO_PORT_K 9
#define GPIO_PORT_L 10
#define GPIO_PORT_M 11
#define GPIO_PORT_N 12
/* discontinuity */
#define GPIO_PORT_P 13
#define GPIO_PORT_Q 14
#endif

13
platform/stellaris/init.c
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@@ -34,6 +34,9 @@ void stellaris_debug_init(void);
void stellaris_timer_early_init(void);
void stellaris_timer_init(void);
void stellaris_gpio_early_init(void);
void stellaris_gpio_init(void);
void platform_early_init(void)
{
//
@@ -48,16 +51,9 @@ void platform_early_init(void)
//
SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_XTAL_16MHZ | SYSCTL_OSC_MAIN);
stellaris_timer_early_init();
/*
wdt_disable(WDT);
pmc_enable_periph_clk(ID_PIOC);
pio_set_output(PIOC, PIO_PC9, 0, 0, 1);
*/
stellaris_gpio_early_init();
stellaris_debug_early_init();
}
@@ -65,6 +61,7 @@ void platform_early_init(void)
void platform_init(void)
{
stellaris_timer_init();
stellaris_gpio_init();
stellaris_debug_init();
}

3
platform/stellaris/rules.mk
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@@ -28,8 +28,9 @@ INCLUDES += \
-I$(LOCAL_DIR)/include \
MODULE_SRCS += \
$(LOCAL_DIR)/init.c \
$(LOCAL_DIR)/debug.c \
$(LOCAL_DIR)/gpio.c \
$(LOCAL_DIR)/init.c \
$(LOCAL_DIR)/timer.c \
$(LOCAL_DIR)/vectab.c \

29
target/stellaris-launchpad/init.c
View File

@@ -24,24 +24,23 @@
#include <debug.h>
#include <target.h>
#include <compiler.h>
#include <dev/gpio.h>
#include <platform/gpio.h>
#include "ti_driverlib.h"
void target_early_init(void)
{
SysCtlPeripheralPowerOn(SYSCTL_PERIPH_GPIOF);
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
GPIOPinWrite(GPIO_PORTF_AHB_BASE, GPIO_PIN_1, 0);
GPIOPinWrite(GPIO_PORTF_AHB_BASE, GPIO_PIN_2, 0);
GPIOPinWrite(GPIO_PORTF_AHB_BASE, GPIO_PIN_3, 0);
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1, 0);
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, 0);
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_3, 0);
GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_1, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_2, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_3, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_1, GPIO_DIR_MODE_OUT);
GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_2, GPIO_DIR_MODE_OUT);
GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT);
GPIOPadConfigSet(GPIO_PORTF_AHB_BASE, GPIO_PIN_1, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet(GPIO_PORTF_AHB_BASE, GPIO_PIN_2, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIOPadConfigSet(GPIO_PORTF_AHB_BASE, GPIO_PIN_3, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
GPIODirModeSet(GPIO_PORTF_AHB_BASE, GPIO_PIN_1, GPIO_DIR_MODE_OUT);
GPIODirModeSet(GPIO_PORTF_AHB_BASE, GPIO_PIN_2, GPIO_DIR_MODE_OUT);
GPIODirModeSet(GPIO_PORTF_AHB_BASE, GPIO_PIN_3, GPIO_DIR_MODE_OUT);
}
void target_init(void)
@@ -51,9 +50,9 @@ void target_init(void)
void target_set_debug_led(unsigned int led, bool on)
{
switch (led) {
case 0: GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1, on ? GPIO_PIN_1 : 0); break;
case 1: GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, on ? GPIO_PIN_2 : 0); break;
case 2: GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_3, on ? GPIO_PIN_3 : 0); break;
case 0: gpio_set(GPIO(GPIO_PORT_F, 1), on); break;
case 1: gpio_set(GPIO(GPIO_PORT_F, 2), on); break;
case 2: gpio_set(GPIO(GPIO_PORT_F, 3), on); break;
}
}