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[platform] update platforms to use new mmu mapping routines

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-Have alterasoc map all of dram as cached
This commit is contained in:
Travis Geiselbrecht
2014-05-01 19:04:38 -07:00
parent 572cae8a4b
commit 3a50dd3591
3 changed files with 26 additions and 5 deletions
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10
platform/alterasoc/platform.c
View File

@@ -22,7 +22,9 @@
*/
#include <err.h>
#include <debug.h>
#include <assert.h>
#include <trace.h>
#include <arch/arm/mmu.h>
#include <dev/uart.h>
#include <dev/interrupt/arm_gic.h>
#include <platform.h>
@@ -30,6 +32,14 @@
void platform_init_mmu_mappings(void)
{
#define MB (1024*1024)
STATIC_ASSERT((MEMBASE % MB) == 0);
STATIC_ASSERT((MEMSIZE % MB) == 0);
/* map dram as full cacheable */
for (addr_t a = MEMBASE; a < MEMSIZE; a += MB) {
arm_mmu_map_section(a, a, MMU_MEMORY_L1_TYPE_NORMAL_WRITE_BACK_ALLOCATE | MMU_MEMORY_L1_AP_P_RW_U_NA);
}
}
void platform_early_init(void)

12
platform/am335x/platform.c
View File

@@ -40,14 +40,20 @@ void platform_init_mmu_mappings(void)
/* do some memory map initialization */
addr_t addr;
arm_mmu_map_section(SDRAM_BASE, 0, MMU_FLAG_CACHED | MMU_FLAG_BUFFERED);
arm_mmu_map_section(SDRAM_BASE, 0,
MMU_MEMORY_L1_TYPE_NORMAL_WRITE_BACK_ALLOCATE |
MMU_MEMORY_L1_AP_P_NA_U_NA);
for (addr=SDRAM_BASE; addr < SDRAM_BASE + SDRAM_SIZE; addr += (1024*1024)) {
arm_mmu_map_section(addr, addr, MMU_FLAG_CACHED | MMU_FLAG_BUFFERED | MMU_FLAG_READWRITE);
arm_mmu_map_section(addr, addr,
MMU_MEMORY_L2_TYPE_NORMAL_WRITE_BACK_ALLOCATE |
MMU_MEMORY_L1_AP_P_RW_U_NA);
}
for (addr=0x40000000; addr < 0x40000000 + (512*1024*1024); addr += (1024*1024)) {
arm_mmu_map_section(addr, addr, MMU_FLAG_READWRITE);
arm_mmu_map_section(addr, addr,
MMU_MEMORY_L1_TYPE_STRONGLY_ORDERED |
MMU_MEMORY_L1_AP_P_RW_U_NA);
}
}

9
platform/omap3/platform.c
View File

@@ -34,9 +34,14 @@ void platform_init_mmu_mappings(void)
{
/* do some memory map initialization */
addr_t addr;
arm_mmu_map_section(SDRAM_BASE, 0, MMU_FLAG_CACHED|MMU_FLAG_BUFFERED);
arm_mmu_map_section(SDRAM_BASE, 0,
MMU_MEMORY_L1_TYPE_NORMAL_WRITE_BACK_ALLOCATE |
MMU_MEMORY_L1_AP_P_NA_U_NA);
for (addr = SDRAM_BASE; addr < SDRAM_BASE + SDRAM_SIZE; addr += (1024*1024)) {
arm_mmu_map_section(addr, addr, MMU_FLAG_CACHED|MMU_FLAG_BUFFERED|MMU_FLAG_READWRITE);
arm_mmu_map_section(addr, addr,
MMU_MEMORY_L2_TYPE_NORMAL_WRITE_BACK_ALLOCATE |
MMU_MEMORY_L1_AP_P_RW_U_NA);
}
}