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[platform][zynq] interrupt driven uart rx

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This commit is contained in:
Travis Geiselbrecht
2014-04-21 01:19:22 -07:00
parent e5a4b14bed
commit 3a463d272d
7 changed files with 199 additions and 51 deletions
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30
platform/zynq/clocks.c Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2014 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <reg.h>
#include <stdio.h>
#include <kernel/thread.h>
#include <platform/debug.h>
#include <platform/zynq.h>
#include <target/debugconfig.h>
#include <reg.h>

55
platform/zynq/debug.c
View File

@@ -20,32 +20,15 @@
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <stdarg.h>
#include <reg.h>
#include <stdio.h>
#include <kernel/thread.h>
#include <dev/uart.h>
#include <platform/debug.h>
#include <platform/zynq.h>
#include <target/debugconfig.h>
#include <reg.h>
#define UART_CR (0x00)
#define UART_MR (0x04)
#define UART_IER (0x08)
#define UART_IDR (0x0c)
#define UART_IMR (0x10)
#define UART_ISR (0x14)
#define UART_BAUDGEN (0x18)
#define UART_RXTOUT (0x1c)
#define UART_RXWM (0x20)
#define UART_MODEMCR (0x24)
#define UART_MODEMSR (0x28)
#define UART_SR (0x2c)
#define UART_FIFO (0x30)
#define UART_BAUD_DIV (0x34)
#define UART_FLOW_DELAY (0x38)
#define UART_TX_FIFO_TRIGGER (0x44)
/* DEBUG_UART must be defined to 0 or 1 */
#if defined(DEBUG_UART) && DEBUG_UART == 0
#define DEBUG_UART_BASE UART0_BASE
@@ -55,8 +38,6 @@
#error define DEBUG_UART to something valid
#endif
#define UARTREG(reg) (*REG32(DEBUG_UART_BASE + (reg)))
#if 0
uboot setup for zynq board
E0001000: 00000114
@@ -82,32 +63,18 @@ E0001044: 00000020
void platform_dputc(char c)
{
if (c == '\n')
platform_dputc('\r');
/* spin while fifo is full */
while (UARTREG(UART_SR) & (1<<4))
;
UARTREG(UART_FIFO) = c;
uart_putc(DEBUG_UART, '\r');
uart_putc(DEBUG_UART, c);
}
int platform_dgetc(char *c, bool wait)
{
if (!wait) {
if (UARTREG(UART_SR) & (1<<1)) {
/* fifo empty */
return -1;
}
*c = UARTREG(UART_FIFO) & 0xff;
return 0;
} else {
while ((UARTREG(UART_SR) & (1<<1))) {
// XXX actually block on interrupt
thread_yield();
}
int ret = uart_getc(DEBUG_UART, wait);
if (ret == -1)
return -1;
*c = ret;
return 0;
*c = UARTREG(UART_FIFO) & 0xff;
return 0;
}
}
void platform_halt(void)
@@ -115,9 +82,3 @@ void platform_halt(void)
arch_disable_ints();
for (;;);
}
void platform_early_init_debug(void)
{
UARTREG(UART_CR) = (1<<4)|(1<<2); // txen,rxen
}

2
platform/zynq/include/platform/zynq.h
View File

@@ -67,7 +67,7 @@
#define TTC0_B_INT 43
#define TTC0_C_INT 44
#define UART0_INT 59
#define UART1_INT 81
#define UART1_INT 82
#define TTC1_A_INT 69
#define TTC2_B_INT 70
#define TTC3_C_INT 71

4
platform/zynq/platform.c
View File

@@ -22,6 +22,7 @@
*/
#include <err.h>
#include <debug.h>
#include <dev/uart.h>
#include <platform.h>
#include "platform_p.h"
@@ -31,7 +32,7 @@ void platform_init_mmu_mappings(void)
void platform_early_init(void)
{
platform_early_init_debug();
uart_init_early();
/* initialize the interrupt controller */
platform_init_interrupts();
@@ -42,5 +43,6 @@ void platform_early_init(void)
void platform_init(void)
{
uart_init();
}

1
platform/zynq/platform_p.h
View File

@@ -23,7 +23,6 @@
#ifndef __PLATFORM_P_H
#define __PLATFORM_P_H
void platform_early_init_debug(void);
void platform_init_interrupts(void);
void platform_init_timer(void);

7
platform/zynq/rules.mk
View File

@@ -5,14 +5,19 @@ MODULE := $(LOCAL_DIR)
ARCH := arm
ARM_CPU := cortex-a9
MODULE_DEPS := \
lib/cbuf
GLOBAL_INCLUDES += \
$(LOCAL_DIR)/include
MODULE_SRCS += \
$(LOCAL_DIR)/clocks.c \
$(LOCAL_DIR)/debug.c \
$(LOCAL_DIR)/interrupts.c \
$(LOCAL_DIR)/platform.c \
$(LOCAL_DIR)/timer.c
$(LOCAL_DIR)/timer.c \
$(LOCAL_DIR)/uart.c
ifeq ($(ZYNQ_USE_SRAM),1)
MEMBASE := 0x0

151
platform/zynq/uart.c Normal file
View File

@@ -0,0 +1,151 @@
/*
* Copyright (c) 2014 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <reg.h>
#include <stdio.h>
#include <trace.h>
#include <lib/cbuf.h>
#include <kernel/thread.h>
#include <platform/interrupts.h>
#include <platform/debug.h>
#include <platform/zynq.h>
#define UART_CR (0x00)
#define UART_MR (0x04)
#define UART_IER (0x08)
#define UART_IDR (0x0c)
#define UART_IMR (0x10)
#define UART_ISR (0x14)
#define UART_BAUDGEN (0x18)
#define UART_RXTOUT (0x1c)
#define UART_RXWM (0x20)
#define UART_MODEMCR (0x24)
#define UART_MODEMSR (0x28)
#define UART_SR (0x2c)
#define UART_FIFO (0x30)
#define UART_BAUD_DIV (0x34)
#define UART_FLOW_DELAY (0x38)
#define UART_TX_FIFO_TRIGGER (0x44)
#define UARTREG(base, reg) (*REG32((base) + (reg)))
#define RXBUF_SIZE 16
static cbuf_t uart0_rx_buf;
static cbuf_t uart1_rx_buf;
static inline uintptr_t uart_to_ptr(unsigned int n) { return (n == 0) ? UART0_BASE : UART1_BASE; }
static inline cbuf_t *uart_to_rxbuf(unsigned int n) { return (n == 0) ? &uart0_rx_buf : &uart1_rx_buf; }
static enum handler_return uart_irq(void *arg)
{
bool resched = false;
uint port = (uint)arg;
uintptr_t base = uart_to_ptr(port);
/* read interrupt status and mask */
uint32_t isr = UARTREG(base, UART_ISR);
isr &= UARTREG(base, UART_IMR);
if (isr & (1<<0)) { // rxtrig
UARTREG(base, UART_ISR) = (1<< 0);
cbuf_t *rxbuf = uart_to_rxbuf(port);
while ((UARTREG(base, UART_SR) & (1<<1)) == 0) {
char c = UARTREG(base, UART_FIFO);
cbuf_write_char(rxbuf, c, false);
resched = true;
}
}
return resched ? INT_RESCHEDULE : INT_NO_RESCHEDULE;
}
void uart_init(void)
{
cbuf_initialize(&uart0_rx_buf, RXBUF_SIZE);
cbuf_initialize(&uart1_rx_buf, RXBUF_SIZE);
register_int_handler(UART0_INT, &uart_irq, (void *)0);
register_int_handler(UART1_INT, &uart_irq, (void *)1);
// clear all irqs
UARTREG(uart_to_ptr(0), UART_IDR) = 0xffffffff;
UARTREG(uart_to_ptr(1), UART_IDR) = 0xffffffff;
UARTREG(uart_to_ptr(0), UART_CR) |= (1<<2); // rxen
UARTREG(uart_to_ptr(1), UART_CR) |= (1<<2); // rxen
// set rx fifo trigger to 1
UARTREG(uart_to_ptr(0), UART_RXWM) = 1;
UARTREG(uart_to_ptr(1), UART_RXWM) = 1;
// enable rx interrupt
UARTREG(uart_to_ptr(0), UART_IER) = (1<<0); // rxtrig
UARTREG(uart_to_ptr(1), UART_IER) = (1<<0); // rxtrig
unmask_interrupt(UART0_INT);
unmask_interrupt(UART1_INT);
}
void uart_init_early(void)
{
UARTREG(uart_to_ptr(0), UART_CR) = (1<<4); // txen
UARTREG(uart_to_ptr(1), UART_CR) = (1<<4); // txen
}
int uart_putc(int port, char c)
{
uintptr_t base = uart_to_ptr(port);
/* spin while fifo is full */
while (UARTREG(base, UART_SR) & (1<<4))
;
UARTREG(base, UART_FIFO) = c;
return 1;
}
int uart_getc(int port, bool wait)
{
cbuf_t *rxbuf = uart_to_rxbuf(port);
char c;
if (cbuf_read_char(rxbuf, &c, wait) == 1)
return c;
return -1;
}
void uart_flush_tx(int port)
{
}
void uart_flush_rx(int port)
{
}
void uart_init_port(int port, uint baud)
{
}