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[zynq] Convert the Zynq PLL init jam table into readable code

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End goal will be to convert all the functions and remove ps7 entirely.
This commit is contained in:
Chris Anderson
2014-07-29 22:24:26 -07:00
parent c56364774e
commit 2b4c03e80e
2 changed files with 106 additions and 29 deletions
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38
platform/zynq/include/platform/zynq.h
View File

@@ -25,6 +25,7 @@
#ifndef ASSEMBLY
#include <reg.h>
#include <compiler.h>
#include <bits.h>
#endif
/* memory addresses */
@@ -306,6 +307,43 @@ STATIC_ASSERT(offsetof(struct slcr_regs, DDRIOB_DCI_STATUS) == 0xb74);
#define SLCR ((struct slcr_regs *)SLCR_BASE)
#define SLCR_REG(reg) (*REG32((uintptr_t)&SLCR->reg))
/* ARM_PLL_CFG */
#define PLL_CFG_PLL_RES(x) ((x & BIT_MASK(4)) << 4)
#define PLL_CFG_PLL_CP(x) ((x & BIT_MASK(4)) << 8)
#define PLL_CFG_LOCK_CNT(x) ((x & BIT_MASK(10)) << 12)
/* DDR_PLL_CFG */
/* ARM_PLL_CTRL and IO_PLL_CTRL */
#define PLL_RESET (1)
#define PLL_PWRDOWN (1 << 1)
#define PLL_BYPASS_QUAL (1 << 3)
#define PLL_BYPASS_FORCE (1 << 4)
#define PLL_FDIV(x) ((x & BIT_MASK(7)) << 12)
/* ARM_CLK_CTRL */
#define ARM_CLK_CTRL_SRCSEL(x) ((x & BIT_MASK(2)) << 4)
#define ARM_CLK_CTRL_DIVISOR(x) ((x & BIT_MASK(6)) << 8)
#define ARM_CLK_CTRL_CPU_6OR4XCLKACT (1 << 24)
#define ARM_CLK_CTRL_CPU_3OR2XCLKACT (1 << 25)
#define ARM_CLK_CTRL_CPU_2XCLKACT (1 << 26)
#define ARM_CLK_CTRL_CPU_1XCLKACT (1 << 27)
#define ARM_CLK_CTRL_PERI_CLKACT (1 << 28)
/* DDR_CLK_CTRL */
#define DDR_CLK_CTRL_DDR_3XCLKACT (1)
#define DDR_CLK_CTRL_DDR_2XCLKACT (1 << 1)
#define DDR_CLK_CTRL_DDR_3XCLK_DIV(x) ((x & BIT_MASK(6)) << 20)
#define DDR_CLK_CTRL_DDR_2XCLK_DIV(x) ((x & BIT_MASK(6)) << 26)
/* PLL_STATUS */
#define PLL_STATUS_ARM_PLL_LOCK (1)
#define PLL_STATUS_DDR_PLL_LOCK (1 << 1)
#define PLL_STATUS_IO_PLL_LOCK (1 << 2)
#define PLL_STATUS_ARM_PLL_STABLE (1 << 3)
#define PLL_STATUS_DDR_PLL_STABLE (1 << 4)
#define PLL_STATUS_IO_PLL_STABLE (1 << 5)
/* MIO pin configuration */
#define MIO_TRI_ENABLE (1)
#define MIO_L0_SEL (1 << 1)

97
target/zybo/init.c
View File

@@ -1,3 +1,4 @@
#include <platform/zynq.h>
/*
* This file is automatically generated
*/
@@ -60,34 +61,72 @@ static void perf_reset_clock(void);
static void perf_reset_and_start_timer(void);
static unsigned int get_number_of_cycles_for_delay(unsigned int delay);
static const unsigned long ps7_pll_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x001772C0U),
EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x0001A000U),
EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U),
EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U),
EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U),
EMIT_MASKPOLL(0XF800010C, 0x00000001U),
EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U),
EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U),
EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x001DB2C0U),
EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00015000U),
EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U),
EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U),
EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U),
EMIT_MASKPOLL(0XF800010C, 0x00000002U),
EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U),
EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U),
EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x001F42C0U),
EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00014000U),
EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U),
EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U),
EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U),
EMIT_MASKPOLL(0XF800010C, 0x00000004U),
EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U),
EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU ,0x0000767BU),
EMIT_EXIT(),
};
static inline int pll_poll(uint32_t mask)
{
uint32_t iters = UINT_MAX;
while (iters-- && !(SLCR_REG(PLL_STATUS) & mask)) ;
if (iters) {
return 0;
}
return -1;
}
int zynq_pll_init(void) {
zynq_slcr_unlock();
/* ARM PLL & Clock config
* 375 cycles needed for pll
* 26 divisor on pll
* enable all ARM clocks
* 2 divisor on ARM clocks
* ARM clock source is ARM PLL
*/
SLCR_REG(ARM_PLL_CFG) = PLL_CFG_LOCK_CNT(375) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(ARM_PLL_CTRL) = PLL_FDIV(26) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_ARM_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(ARM_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(ARM_CLK_CTRL) = ARM_CLK_CTRL_DIVISOR(2) | ARM_CLK_CTRL_CPU_6OR4XCLKACT |
ARM_CLK_CTRL_CPU_3OR2XCLKACT | ARM_CLK_CTRL_CPU_2XCLKACT |
ARM_CLK_CTRL_CPU_1XCLKACT |ARM_CLK_CTRL_PERI_CLKACT;
/* DDR PLL & Clock config
* 475 cycles needed
* 21 divisor on PLL
* enable all DDR clocks
* 2 divisor for 3XCLK, 3 divisor for 2XCLK
*/
SLCR_REG(DDR_PLL_CFG) = PLL_CFG_LOCK_CNT(475) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(DDR_PLL_CTRL) = PLL_FDIV(26) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_DDR_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(DDR_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
SLCR_REG(DDR_CLK_CTRL) = DDR_CLK_CTRL_DDR_3XCLKACT | DDR_CLK_CTRL_DDR_2XCLKACT | DDR_CLK_CTRL_DDR_3XCLK_DIV(3) | DDR_CLK_CTRL_DDR_2XCLK_DIV(2);
/* IO PLL config */
SLCR_REG(IO_PLL_CFG) = PLL_CFG_LOCK_CNT(0x1F4) | PLL_CFG_PLL_CP(2) | PLL_CFG_PLL_RES(12);
SLCR_REG(IO_PLL_CTRL) = PLL_FDIV(20) | PLL_BYPASS_FORCE | PLL_RESET;
SLCR_REG(IO_PLL_CTRL) &= ~PLL_RESET;
if (pll_poll(PLL_STATUS_IO_PLL_LOCK) == -1) {
return -1;
}
SLCR_REG(IO_PLL_CTRL) &= ~PLL_BYPASS_FORCE;
zynq_slcr_lock();
return 0;
}
static const unsigned long ps7_clock_init_data_3_0[] = {
EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU ,0x0000DF0DU),
@@ -392,7 +431,7 @@ int ps7_init(void)
if (ret != PS7_INIT_SUCCESS) return ret;
// PLL init
ret = ps7_config (ps7_pll_init_data_3_0);
ret = zynq_pll_init();
if (ret != PS7_INIT_SUCCESS) return ret;
// Clock init