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[arch][riscv] remove the last of the RISCV_BOOT_HART mechanism

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Now the harts are dynamically numbered, so don't need
this mechanism anymore.
This commit is contained in:
Travis Geiselbrecht
2020-12-30 01:09:24 -08:00
parent c2d77234c3
commit 1e50428091
5 changed files with 8 additions and 23 deletions
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2
arch/riscv/arch.c
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@@ -21,7 +21,7 @@
#define LOCAL_TRACE 0
// per cpu structure, pointed to by xscratch
struct riscv_percpu percpu[RISCV_MAX_HARTS];
struct riscv_percpu percpu[SMP_MAX_CPUS];
// called extremely early from start.S prior to getting into any other C code on
// both the boot cpu and the secondaries

2
arch/riscv/include/arch/riscv.h
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@@ -154,7 +154,7 @@ struct riscv_percpu {
uint hart_id;
} __ALIGNED(CACHE_LINE);
extern struct riscv_percpu percpu[RISCV_MAX_HARTS];
extern struct riscv_percpu percpu[SMP_MAX_CPUS];
static inline struct riscv_percpu *riscv_get_percpu(void) {
return (struct riscv_percpu *)riscv_csr_read(RISCV_CSR_XSCRATCH);

19
arch/riscv/mp.c
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@@ -26,19 +26,11 @@
#define LOCAL_TRACE 0
// Highest supported HART has to at least be more than number of
// cpus we support. Generally they're the same, but some cpus may start
// at nonzero hart ids.
STATIC_ASSERT(RISCV_MAX_HARTS >= SMP_MAX_CPUS);
// boot hart has to be one of the valid ones
STATIC_ASSERT(RISCV_BOOT_HART < RISCV_MAX_HARTS);
// mapping of cpu -> hart
static int cpu_to_hart_map[SMP_MAX_CPUS];
// list of IPIs queued per cpu
static volatile int ipi_data[RISCV_MAX_HARTS];
static volatile int ipi_data[SMP_MAX_CPUS];
static spin_lock_t boot_cpu_lock = 1;
volatile int secondaries_to_init = SMP_MAX_CPUS - 1;
@@ -73,17 +65,18 @@ status_t arch_mp_send_ipi(mp_cpu_mask_t target, mp_ipi_t ipi) {
// software triggered exceptions, used for cross-cpu calls
enum handler_return riscv_software_exception(void) {
uint ch = riscv_current_hart();
uint curr_cpu = arch_curr_cpu_num();
#if RISCV_M_MODE
uint ch = riscv_current_hart();
clint_ipi_clear(ch);
#else
sbi_clear_ipi();
#endif
rmb();
int reason = atomic_swap(&ipi_data[ch], 0);
LTRACEF("ch %u reason %#x\n", ch, reason);
int reason = atomic_swap(&ipi_data[curr_cpu], 0);
LTRACEF("cpu %u reason %#x\n", curr_cpu, reason);
enum handler_return ret = INT_NO_RESCHEDULE;
if (reason & (1u << MP_IPI_RESCHEDULE)) {
@@ -96,7 +89,7 @@ enum handler_return riscv_software_exception(void) {
}
if (unlikely(reason)) {
TRACEF("unhandled ipi cause %#x, hartid %#x\n", reason, ch);
TRACEF("unhandled ipi cause %#x, cpu %u\n", reason, curr_cpu);
panic("stopping");
}

4
arch/riscv/rules.mk
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@@ -15,13 +15,9 @@ MODULE_SRCS += $(LOCAL_DIR)/time.c
MODULE_CFLAGS += -Wno-override-init
SMP_MAX_CPUS ?= 1
RISCV_MAX_HARTS ?= $(SMP_MAX_CPUS)
RISCV_BOOT_HART ?= 0
RISCV_MMU ?= none
GLOBAL_DEFINES += SMP_MAX_CPUS=$(SMP_MAX_CPUS)
GLOBAL_DEFINES += RISCV_MAX_HARTS=$(RISCV_MAX_HARTS)
GLOBAL_DEFINES += RISCV_BOOT_HART=$(RISCV_BOOT_HART)
GLOBAL_DEFINES += PLATFORM_HAS_DYNAMIC_TIMER=1
ifeq ($(WITH_SMP),1)

4
target/sifive-unleashed/rules.mk
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@@ -5,10 +5,6 @@ PLATFORM := sifive
VARIANT := sifive_u
WITH_SMP := 1
RISCV_BOOT_HART := 1
# Hart 0 on this board is disabled in supervisor mode, so make sure
# there are enough hart slots for it
RISCV_MAX_HARTS := 5
GLOBAL_DEFINES += SIFIVE_FREQ=500000000 # 500 MHz