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[arch][arm] Add an API to read and write 64-bit cp15 registers

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Bug: 138743238
Change-Id: Ic6cd97f2b7d291b91b9c873e8819988bafa08573
This commit is contained in:
Michael Ryleev
2019-11-13 10:28:01 -08:00
committed by Travis Geiselbrecht
parent 52fd0d0273
commit 1d283e66c6
1 changed files with 25 additions and 0 deletions
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25
arch/arm/include/arch/arm.h
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@@ -123,12 +123,37 @@ static inline __ALWAYS_INLINE void arm_write_##reg##_relaxed(uint32_t val) { \
__asm__ volatile("mcr " #cp ", " #op1 ", %0, " #c1 "," #c2 "," #op2 :: "r" (val)); \
}
#define GEN_CP_REG64_FUNCS(cp, reg, op1, crm) \
static inline __ALWAYS_INLINE uint32_t arm_read_##reg(void) { \
uint64_t _val; \
__asm__ volatile("mrrc " #cp ", " #op1 ", %0, %H0, " #crm : "=r" (_val)); \
return _val; \
} \
\
static inline __ALWAYS_INLINE uint32_t arm_read_##reg##_relaxed(void) { \
uint64_t _val; \
__asm__("mrrc " #cp ", " #op1 ", %0, %H0, " #crm : "=r" (_val)); \
return _val; \
} \
\
static inline __ALWAYS_INLINE void arm_write_##reg(uint64_t val) { \
__asm__ volatile("mcrr " #cp ", " #op1 ", %0, %H0, " #crm :: "r" (val)); \
ISB; \
} \
\
static inline __ALWAYS_INLINE void arm_write_##reg##_relaxed(uint64_t val) { \
__asm__ volatile("mcrr " #cp ", " #op1 ", %0, %H0, " #crm :: "r" (val)); \
}
#define GEN_CP15_REG_FUNCS(reg, op1, c1, c2, op2) \
GEN_CP_REG_FUNCS(p15, reg, op1, c1, c2, op2)
#define GEN_CP14_REG_FUNCS(reg, op1, c1, c2, op2) \
GEN_CP_REG_FUNCS(p14, reg, op1, c1, c2, op2)
#define GEN_CP15_REG64_FUNCS(reg, op1, crm) \
GEN_CP_REG64_FUNCS(p15, reg, op1, crm)
/* armv6+ control regs */
GEN_CP15_REG_FUNCS(sctlr, 0, c1, c0, 0);
GEN_CP15_REG_FUNCS(actlr, 0, c1, c0, 1);