[arch][arm64] Add cache-ops

Change-Id: I49b4279a3019587f4d8e5cb7a766b0b118a99301

arch/arm64/cache-ops.S

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2014, Google Inc. All rights reserved
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <asm.h>
+#include <arch/ops.h>
+#include <arch/defines.h>
+
+.text
+
+.macro cache_range_op, cache op
+    add     x2, x0, x1                  // calculate the end address
+    bic     x3, x0, #(CACHE_LINE-1)     // align the start with a cache line
+.Lcache_range_op_loop\@:
+    \cache  \op, x3
+    add     x3, x3, #CACHE_LINE
+    cmp     x3, x2
+    blo     .Lcache_range_op_loop\@
+    dsb     sy
+.endm
+
+    /* void arch_flush_cache_range(addr_t start, size_t len); */
+FUNCTION(arch_clean_cache_range)
+    cache_range_op dc cvac         // clean cache to PoC by MVA
+    ret
+
+    /* void arch_flush_invalidate_cache_range(addr_t start, size_t len); */
+FUNCTION(arch_clean_invalidate_cache_range)
+    cache_range_op dc civac        // clean & invalidate dcache to PoC by MVA
+    ret
+
+    /* void arch_invalidate_cache_range(addr_t start, size_t len); */
+FUNCTION(arch_invalidate_cache_range)
+    cache_range_op dc ivac         // invalidate dcache to PoC by MVA
+    ret
+
+    /* void arch_sync_cache_range(addr_t start, size_t len); */
+FUNCTION(arch_sync_cache_range)
+    cache_range_op dc cvau         // clean dcache to PoU by MVA
+    cache_range_op ic ivau         // invalidate icache to PoU by MVA
+    ret

arch/arm64/rules.mk

@@ -18,9 +18,9 @@ MODULE_SRCS += \
 	$(LOCAL_DIR)/thread.c \
 	$(LOCAL_DIR)/spinlock.S \
 	$(LOCAL_DIR)/start.S \
+	$(LOCAL_DIR)/cache-ops.S \
 
 #	$(LOCAL_DIR)/arm/start.S \
-	$(LOCAL_DIR)/arm/cache-ops.S \
 	$(LOCAL_DIR)/arm/cache.c \
 	$(LOCAL_DIR)/arm/ops.S \
 	$(LOCAL_DIR)/arm/faults.c \