[arch][riscv] move the iframe definitions into a separate header and add syscall support
This commit is contained in:
Travis Geiselbrecht
111
arch/riscv/asm.S
111
arch/riscv/asm.S
@@ -8,6 +8,7 @@
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#include <lk/asm.h>
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#include <arch/riscv.h>
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#include <arch/riscv/asm.h>
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#include <arch/riscv/iframe.h>
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/* void riscv_context_switch(
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struct riscv_context_switch_frame *oldcs,
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@@ -49,17 +50,17 @@ FUNCTION(riscv_context_switch)
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END_FUNCTION(riscv_context_switch)
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.macro save_regs, user
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addi sp, sp, -REGOFF(24) // subtract a multiple of 16 to align the stack in 32bit
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addi sp, sp, -RISCV_IFRAME_LEN // subtract a multiple of 16 to align the stack in 32bit
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.if \user == 1
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// recover tp from the top of the stack (we saved it here before)
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STR tp, REGOFF(18)(sp)
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LDR tp, REGOFF(23)(sp) // this is where the top of the stack used to be
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STR tp, RISCV_IFRAME_TP(sp)
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LDR tp, (RISCV_IFRAME_LEN-__riscv_xlen / 8)(sp) // this is where the top of the stack used to be
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STR gp, REGOFF(19)(sp)
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STR gp, RISCV_IFRAME_GP(sp)
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// save the user stack and zero scratch register
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csrrw gp, RISCV_CSR_XSCRATCH, zero
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STR gp, REGOFF(20)(sp)
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STR gp, RISCV_IFRAME_SP(sp)
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// recover gp for the kernel
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.option push
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@@ -67,27 +68,27 @@ END_FUNCTION(riscv_context_switch)
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lla gp, __global_pointer$
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.option pop
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.endif
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STR t6, REGOFF(17)(sp)
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STR t5, REGOFF(16)(sp)
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STR t4, REGOFF(15)(sp)
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STR t3, REGOFF(14)(sp)
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STR t2, REGOFF(13)(sp)
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STR t1, REGOFF(12)(sp)
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STR t0, REGOFF(11)(sp)
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STR a7, REGOFF(10)(sp)
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STR a6, REGOFF(9)(sp)
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STR a5, REGOFF(8)(sp)
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STR a4, REGOFF(7)(sp)
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STR a3, REGOFF(6)(sp)
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STR a2, REGOFF(5)(sp)
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STR a1, REGOFF(4)(sp)
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STR a0, REGOFF(3)(sp)
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STR ra, REGOFF(2)(sp)
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STR t6, RISCV_IFRAME_T(6)(sp)
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STR t5, RISCV_IFRAME_T(5)(sp)
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STR t4, RISCV_IFRAME_T(4)(sp)
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STR t3, RISCV_IFRAME_T(3)(sp)
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STR t2, RISCV_IFRAME_T(2)(sp)
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STR t1, RISCV_IFRAME_T(1)(sp)
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STR t0, RISCV_IFRAME_T(0)(sp)
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STR a7, RISCV_IFRAME_A(7)(sp)
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STR a6, RISCV_IFRAME_A(6)(sp)
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STR a5, RISCV_IFRAME_A(5)(sp)
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STR a4, RISCV_IFRAME_A(4)(sp)
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STR a3, RISCV_IFRAME_A(3)(sp)
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STR a2, RISCV_IFRAME_A(2)(sp)
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STR a1, RISCV_IFRAME_A(1)(sp)
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STR a0, RISCV_IFRAME_A(0)(sp)
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STR ra, RISCV_IFRAME_RA(sp)
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csrr t0, RISCV_CSR_XSTATUS
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STR t0, REGOFF(1)(sp)
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STR t0, RISCV_IFRAME_STATUS(sp)
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csrr a0, RISCV_CSR_XCAUSE
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csrr a1, RISCV_CSR_XEPC
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STR a1, REGOFF(0)(sp)
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STR a1, RISCV_IFRAME_EPC(sp)
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mv a2, sp
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// args are set up for a call into riscv_exception_handler()
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// a0 = xcause
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@@ -97,63 +98,63 @@ END_FUNCTION(riscv_context_switch)
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.macro restore_regs, user
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// put everything back
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LDR t0, REGOFF(0)(sp)
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LDR t0, RISCV_IFRAME_EPC(sp)
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csrw RISCV_CSR_XEPC, t0
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LDR t0, REGOFF(1)(sp)
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LDR t0, RISCV_IFRAME_STATUS(sp)
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csrw RISCV_CSR_XSTATUS, t0
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LDR ra, REGOFF(2)(sp)
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LDR a0, REGOFF(3)(sp)
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LDR a1, REGOFF(4)(sp)
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LDR a2, REGOFF(5)(sp)
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LDR a3, REGOFF(6)(sp)
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LDR a4, REGOFF(7)(sp)
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LDR a5, REGOFF(8)(sp)
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LDR a6, REGOFF(9)(sp)
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LDR a7, REGOFF(10)(sp)
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LDR t0, REGOFF(11)(sp)
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LDR t1, REGOFF(12)(sp)
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LDR t2, REGOFF(13)(sp)
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LDR t3, REGOFF(14)(sp)
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LDR t4, REGOFF(15)(sp)
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LDR t5, REGOFF(16)(sp)
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LDR t6, REGOFF(17)(sp)
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LDR ra, RISCV_IFRAME_RA(sp)
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LDR a0, RISCV_IFRAME_A(0)(sp)
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LDR a1, RISCV_IFRAME_A(1)(sp)
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LDR a2, RISCV_IFRAME_A(2)(sp)
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LDR a3, RISCV_IFRAME_A(3)(sp)
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LDR a4, RISCV_IFRAME_A(4)(sp)
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LDR a5, RISCV_IFRAME_A(5)(sp)
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LDR a6, RISCV_IFRAME_A(6)(sp)
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LDR a7, RISCV_IFRAME_A(7)(sp)
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LDR t0, RISCV_IFRAME_T(0)(sp)
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LDR t1, RISCV_IFRAME_T(1)(sp)
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LDR t2, RISCV_IFRAME_T(2)(sp)
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LDR t3, RISCV_IFRAME_T(3)(sp)
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LDR t4, RISCV_IFRAME_T(4)(sp)
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LDR t5, RISCV_IFRAME_T(5)(sp)
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LDR t6, RISCV_IFRAME_T(6)(sp)
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.if \user == 1
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// before we run out of registers, save tp to the top of the kernel stack
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// and put the kernel stack in the scratch register
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addi gp, sp, REGOFF(24)
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addi gp, sp, RISCV_IFRAME_LEN
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STR tp, REGOFF(-1)(gp)
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csrw RISCV_CSR_XSCRATCH, sp
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csrw RISCV_CSR_XSCRATCH, gp
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LDR tp, REGOFF(18)(sp)
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LDR gp, REGOFF(19)(sp)
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LDR sp, REGOFF(20)(sp)
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LDR tp, RISCV_IFRAME_TP(sp)
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LDR gp, RISCV_IFRAME_GP(sp)
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LDR sp, RISCV_IFRAME_SP(sp)
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.else
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addi sp, sp, REGOFF(24)
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addi sp, sp, RISCV_IFRAME_LEN
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.endif
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.endm
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/* top level exception handler for riscv in non vectored mode */
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// top level exception handler for riscv in non vectored mode
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.balign 4
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FUNCTION(riscv_exception_entry)
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/* check to see if we came from user space */
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// check to see if we came from user space
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csrrw sp, RISCV_CSR_XSCRATCH, sp
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bnez sp, 1f
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/* put the stack back */
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// put the stack back
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csrrw sp, RISCV_CSR_XSCRATCH, sp
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j kernel_exception_entry
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1:
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/* came from user space */
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// came from user space
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j user_exception_entry
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END_FUNCTION(riscv_exception_entry)
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LOCAL_FUNCTION(kernel_exception_entry)
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/* we came from kernel space so tp and gp are okay */
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// we came from kernel space so tp and gp are okay
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save_regs 0
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/* bool kernel = true */
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// bool kernel = true
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li a3, 1
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jal riscv_exception_handler
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@@ -163,10 +164,10 @@ LOCAL_FUNCTION(kernel_exception_entry)
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END_FUNCTION(kernel_exception_entry)
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LOCAL_FUNCTION(user_exception_entry)
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/* we came from user space, assume gp and tp have been trashed */
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// we came from user space, assume gp and tp have been trashed
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save_regs 1
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/* bool kernel = false */
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// bool kernel = false
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li a3, 0
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jal riscv_exception_handler
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@@ -11,37 +11,10 @@
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#include <arch/riscv.h>
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#include <kernel/thread.h>
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#include <platform.h>
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#include <arch/riscv/iframe.h>
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#define LOCAL_TRACE 0
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// keep in sync with asm.S
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struct riscv_short_iframe {
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ulong epc;
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ulong status;
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ulong ra;
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ulong a0;
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ulong a1;
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ulong a2;
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ulong a3;
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ulong a4;
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ulong a5;
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ulong a6;
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ulong a7;
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ulong t0;
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ulong t1;
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ulong t2;
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ulong t3;
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ulong t4;
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ulong t5;
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ulong t6;
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// if we came from user space these are valid
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ulong tp;
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ulong gp;
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ulong sp;
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ulong pad[3];
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};
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static_assert(sizeof(struct riscv_short_iframe) % 16 == 0, "");
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extern enum handler_return riscv_platform_irq(void);
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extern enum handler_return riscv_software_exception(void);
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@@ -79,6 +52,16 @@ static const char *cause_to_string(long cause) {
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return "Unknown";
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}
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static void dump_iframe(struct riscv_short_iframe *frame, bool kernel) {
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printf("a0 %#16lx a1 %#16lx a2 %#16lx a3 %#16lx\n", frame->a0, frame->a1, frame->a2, frame->a3);
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printf("a4 %#16lx a5 %#16lx a6 %#16lx a7 %#16lx\n", frame->a4, frame->a5, frame->a6, frame->a7);
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printf("t0 %#16lx t1 %#16lx t2 %#16lx t3 %#16lx\n", frame->t0, frame->t1, frame->t2, frame->t3);
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printf("t5 %#16lx t6 %#16lx\n", frame->t5, frame->t6);
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if (!kernel) {
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printf("gp %#16lx tp %#16lx sp %#lx\n", frame->gp, frame->tp, frame->sp);
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}
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}
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__NO_RETURN __NO_INLINE
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static void fatal_exception(long cause, ulong epc, struct riscv_short_iframe *frame, bool kernel) {
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if (cause < 0) {
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@@ -89,14 +72,15 @@ static void fatal_exception(long cause, ulong epc, struct riscv_short_iframe *fr
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cause_to_string(cause), epc, riscv_csr_read(RISCV_CSR_XTVAL));
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}
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printf("a0 %#16lx a1 %#16lx a2 %#16lx a3 %#16lx\n", frame->a0, frame->a1, frame->a2, frame->a3);
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printf("a4 %#16lx a5 %#16lx a6 %#16lx a7 %#16lx\n", frame->a4, frame->a5, frame->a6, frame->a7);
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printf("t0 %#16lx t1 %#16lx t2 %#16lx t3 %#16lx\n", frame->t0, frame->t1, frame->t2, frame->t3);
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printf("t5 %#16lx t6 %#16lx\n", frame->t5, frame->t6);
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if (!kernel) {
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printf("gp %#16lx tp %#16lx sp %#lx\n", frame->gp, frame->tp, frame->sp);
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}
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dump_iframe(frame, kernel);
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platform_halt(HALT_ACTION_HALT, HALT_REASON_SW_PANIC);
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}
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// weak reference, can override this somewhere else
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__WEAK
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void riscv_syscall_handler(struct riscv_short_iframe *frame) {
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printf("unhandled syscall handler\n");
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dump_iframe(frame, false);
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platform_halt(HALT_ACTION_HALT, HALT_REASON_SW_PANIC);
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}
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@@ -126,6 +110,9 @@ void riscv_exception_handler(long cause, ulong epc, struct riscv_short_iframe *f
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} else {
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// all synchronous traps go here
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switch (cause) {
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case RISCV_EXCEPTION_ENV_CALL_U_MODE: // ecall from user mode
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riscv_syscall_handler(frame);
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break;
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default:
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fatal_exception(cause, epc, frame, kernel);
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}
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64
arch/riscv/include/arch/riscv/iframe.h
Normal file
64
arch/riscv/include/arch/riscv/iframe.h
Normal file
@@ -0,0 +1,64 @@
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/*
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* Copyright (c) 2021 Travis Geiselbrecht
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*
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* Use of this source code is governed by a MIT-style
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* license that can be found in the LICENSE file or at
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* https://opensource.org/licenses/MIT
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*/
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#pragma once
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#define RISCV_IFRAME_EPC (0 * __riscv_xlen / 8)
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#define RISCV_IFRAME_STATUS (1 * __riscv_xlen / 8)
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#define RISCV_IFRAME_RA (2 * __riscv_xlen / 8)
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#define RISCV_IFRAME_A_BASE (3 * __riscv_xlen / 8)
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#define RISCV_IFRAME_A(n) (RISCV_IFRAME_A_BASE + (n) * __riscv_xlen / 8)
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#define RISCV_IFRAME_T_BASE (11 * __riscv_xlen / 8)
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#define RISCV_IFRAME_T(n) (RISCV_IFRAME_T_BASE + (n) * __riscv_xlen / 8)
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#define RISCV_IFRAME_TP (18 * __riscv_xlen / 8)
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#define RISCV_IFRAME_GP (19 * __riscv_xlen / 8)
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#define RISCV_IFRAME_SP (20 * __riscv_xlen / 8)
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#define RISCV_IFRAME_LEN (24 * __riscv_xlen / 8)
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#ifndef ASSEMBLY
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// keep in sync with asm.S
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struct riscv_short_iframe {
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unsigned long epc;
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unsigned long status;
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unsigned long ra;
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unsigned long a0;
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unsigned long a1;
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unsigned long a2;
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unsigned long a3;
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unsigned long a4;
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unsigned long a5;
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unsigned long a6;
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unsigned long a7;
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unsigned long t0;
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unsigned long t1;
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unsigned long t2;
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unsigned long t3;
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unsigned long t4;
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unsigned long t5;
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unsigned long t6;
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// if we came from user space these are valid
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unsigned long tp;
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unsigned long gp;
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unsigned long sp;
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unsigned long pad[3]; // always maintain a padding of a multiple of 16 bytes
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};
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static_assert(sizeof(struct riscv_short_iframe) % 16 == 0, "");
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static_assert(sizeof(struct riscv_short_iframe) == RISCV_IFRAME_LEN, "");
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static_assert(offsetof(struct riscv_short_iframe, epc) == RISCV_IFRAME_EPC, "");
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static_assert(offsetof(struct riscv_short_iframe, status) == RISCV_IFRAME_STATUS, "");
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static_assert(offsetof(struct riscv_short_iframe, ra) == RISCV_IFRAME_RA, "");
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static_assert(offsetof(struct riscv_short_iframe, a0) == RISCV_IFRAME_A_BASE, "");
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static_assert(offsetof(struct riscv_short_iframe, t0) == RISCV_IFRAME_T_BASE, "");
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static_assert(offsetof(struct riscv_short_iframe, gp) == RISCV_IFRAME_GP, "");
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static_assert(offsetof(struct riscv_short_iframe, sp) == RISCV_IFRAME_SP, "");
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#endif // __ASSEMBLY__
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