lby/lk
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[arch][arm][mmu] Fix read-only mappings

Browse Source 
Update header file to define missing access permission flags for
privileged read-only with unprivileged read-only or unprivileged
no-access.

Also mark P_RW_U_RO masks as obsolete as they are not compatible
with using AP0 as an access flag.

Change-Id: I51504481514ce5344f96f77fcc2cde28c99f825f
This commit is contained in:
Arve Hjønnevåg
2015-08-17 20:28:09 -07:00
committed by Travis Geiselbrecht
parent c80cdf9fee
commit 14de7b0168
2 changed files with 26 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
arch/arm/arm/mmu.c
View File

@@ -76,14 +76,13 @@ static uint32_t mmu_flags_to_l1_arch_flags(uint flags)
arch_flags |= MMU_MEMORY_L1_AP_P_RW_U_NA;
break;
case ARCH_MMU_FLAG_PERM_RO:
/* this mapping is a lie, we don't support RO kernel mapping */
arch_flags |= MMU_MEMORY_L1_AP_P_RW_U_NA;
arch_flags |= MMU_MEMORY_L1_AP_P_RO_U_NA;
break;
case ARCH_MMU_FLAG_PERM_USER:
arch_flags |= MMU_MEMORY_L1_AP_P_RW_U_RW;
break;
case ARCH_MMU_FLAG_PERM_USER | ARCH_MMU_FLAG_PERM_RO:
arch_flags |= MMU_MEMORY_L1_AP_P_RW_U_RO;
arch_flags |= MMU_MEMORY_L1_AP_P_RO_U_RO;
break;
}
@@ -129,14 +128,13 @@ static uint32_t mmu_flags_to_l2_arch_flags_small_page(uint flags)
arch_flags |= MMU_MEMORY_L2_AP_P_RW_U_NA;
break;
case ARCH_MMU_FLAG_PERM_RO:
/* this mapping is a lie, we don't support RO kernel mapping */
arch_flags |= MMU_MEMORY_L2_AP_P_RW_U_NA;
arch_flags |= MMU_MEMORY_L2_AP_P_RO_U_NA;
break;
case ARCH_MMU_FLAG_PERM_USER:
arch_flags |= MMU_MEMORY_L2_AP_P_RW_U_RW;
break;
case ARCH_MMU_FLAG_PERM_USER | ARCH_MMU_FLAG_PERM_RO:
arch_flags |= MMU_MEMORY_L2_AP_P_RW_U_RO;
arch_flags |= MMU_MEMORY_L2_AP_P_RO_U_RO;
break;
}
@@ -252,13 +250,13 @@ status_t arch_mmu_query(vaddr_t vaddr, paddr_t *paddr, uint *flags)
break;
}
switch (tt_entry & MMU_MEMORY_L1_AP_MASK) {
case MMU_MEMORY_L1_AP_P_NA_U_NA:
// XXX no access, what to return?
case MMU_MEMORY_L1_AP_P_RO_U_NA:
*flags |= ARCH_MMU_FLAG_PERM_RO;
break;
case MMU_MEMORY_L1_AP_P_RW_U_NA:
break;
case MMU_MEMORY_L1_AP_P_RW_U_RO:
*flags |= ARCH_MMU_FLAG_PERM_USER | ARCH_MMU_FLAG_PERM_RO; // XXX should it be rw anyway since kernel can rw it?
case MMU_MEMORY_L1_AP_P_RO_U_RO:
*flags |= ARCH_MMU_FLAG_PERM_USER | ARCH_MMU_FLAG_PERM_RO;
break;
case MMU_MEMORY_L1_AP_P_RW_U_RW:
*flags |= ARCH_MMU_FLAG_PERM_USER;
@@ -303,13 +301,13 @@ status_t arch_mmu_query(vaddr_t vaddr, paddr_t *paddr, uint *flags)
break;
}
switch (l2_entry & MMU_MEMORY_L2_AP_MASK) {
case MMU_MEMORY_L2_AP_P_NA_U_NA:
// XXX no access, what to return?
case MMU_MEMORY_L2_AP_P_RO_U_NA:
*flags |= ARCH_MMU_FLAG_PERM_RO;
break;
case MMU_MEMORY_L2_AP_P_RW_U_NA:
break;
case MMU_MEMORY_L2_AP_P_RW_U_RO:
*flags |= ARCH_MMU_FLAG_PERM_USER | ARCH_MMU_FLAG_PERM_RO; // XXX should it be rw anyway since kernel can rw it?
case MMU_MEMORY_L2_AP_P_RO_U_RO:
*flags |= ARCH_MMU_FLAG_PERM_USER | ARCH_MMU_FLAG_PERM_RO;
break;
case MMU_MEMORY_L2_AP_P_RW_U_RW:
*flags |= ARCH_MMU_FLAG_PERM_USER;

20
arch/arm/include/arch/arm/mmu.h
View File

@@ -74,13 +74,17 @@
* | AP P U |
* +-------------------------+
* | |
* | 00 NA NA |
* | 000 NA NA |
* | |
* | 01 RW NA |
* | 001 RW NA |
* | |
* | 10 RW R |
* | 010 RW R |
* | |
* | 11 RW RW |
* | 011 RW RW |
* | |
* | 101 R NA |
* | |
* | 111 R R |
* | |
* +-------------------------+
*
@@ -93,15 +97,19 @@
*
*/
#define MMU_MEMORY_L1_AP_P_NA_U_NA ((0x0 << 15) | (0x0 << 10))
#define MMU_MEMORY_L1_AP_P_RW_U_RO ((0x0 << 15) | (0x2 << 10))
#define MMU_MEMORY_L1_AP_P_RW_U_RO ((0x0 << 15) | (0x2 << 10)) /* Obsolete */
#define MMU_MEMORY_L1_AP_P_RW_U_RW ((0x0 << 15) | (0x3 << 10))
#define MMU_MEMORY_L1_AP_P_RW_U_NA ((0x0 << 15) | (0x1 << 10))
#define MMU_MEMORY_L1_AP_P_RO_U_RO ((0x1 << 15) | (0x3 << 10))
#define MMU_MEMORY_L1_AP_P_RO_U_NA ((0x1 << 15) | (0x1 << 10))
#define MMU_MEMORY_L1_AP_MASK ((0x1 << 15) | (0x3 << 10))
#define MMU_MEMORY_L2_AP_P_NA_U_NA ((0x0 << 9) | (0x0 << 4))
#define MMU_MEMORY_L2_AP_P_RW_U_RO ((0x0 << 9) | (0x2 << 4))
#define MMU_MEMORY_L2_AP_P_RW_U_RO ((0x0 << 9) | (0x2 << 4)) /* Obsolete */
#define MMU_MEMORY_L2_AP_P_RW_U_RW ((0x0 << 9) | (0x3 << 4))
#define MMU_MEMORY_L2_AP_P_RW_U_NA ((0x0 << 9) | (0x1 << 4))
#define MMU_MEMORY_L2_AP_P_RO_U_RO ((0x1 << 9) | (0x3 << 4))
#define MMU_MEMORY_L2_AP_P_RO_U_NA ((0x1 << 9) | (0x1 << 4))
#define MMU_MEMORY_L2_AP_MASK ((0x1 << 9) | (0x3 << 4))
#define MMU_MEMORY_L1_PAGETABLE_NON_SECURE (1 << 3)