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[arch][arm] ARM-m threading support

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This commit is contained in:
Travis Geiselbrecht
2012-04-10 14:19:16 -07:00
parent 57eb824ee9
commit 1286b6b149
11 changed files with 506 additions and 35 deletions
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63
arch/arm/arm-m/arch.c
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@@ -25,12 +25,56 @@
#include <arch/ops.h>
#include <arch/arm.h>
#include <platform.h>
#include <arch/arm/cm3.h>
extern void *vectab;
extern int _end_of_ram;
void *_heap_end = &_end_of_ram;
unsigned int cm3_num_irq_pri_bits;
unsigned int cm3_irq_pri_mask;
void arch_early_init(void)
{
arch_disable_ints();
/* set the vector table base */
SCB->VTOR = (uint32_t)&vectab;
/* clear any pending interrupts and set all the vectors to medium priority */
int i;
int groups = InterruptType->ICTR & 0xf;
for (i = 0; i < groups; i++) {
NVIC->ICER[i] = 0xffffffff;
NVIC->ICPR[i] = 0xffffffff;
NVIC->IP[i*4] = 128; /* medium priority */
NVIC->IP[i*4+1] = 128; /* medium priority */
NVIC->IP[i*4+2] = 128; /* medium priority */
NVIC->IP[i*4+3] = 128; /* medium priority */
}
/* number of priorities */
for (i=0; i < 7; i++) {
__set_BASEPRI(1 << i);
if (__get_BASEPRI() != 0)
break;
}
cm3_num_irq_pri_bits = 8 - i;
cm3_irq_pri_mask = ~((1 << i) - 1) & 0xff;
/* leave BASEPRI at 0 */
__set_BASEPRI(0);
/* set priority grouping to 0 */
NVIC_SetPriorityGrouping(0);
/* enable certain faults */
SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk);
/* set the svc and pendsv priority level to pretty low */
SCB->SHP[11-4] = cm3_lowest_priority();
SCB->SHP[14-4] = cm3_lowest_priority();
}
void arch_init(void)
@@ -45,3 +89,22 @@ void arch_idle(void)
{
}
void cm3_set_irqpri(uint32_t pri)
{
if (pri == 0) {
__disable_irq(); // cpsid i
__set_BASEPRI(0);
} else if (pri >= 256) {
__set_BASEPRI(0);
__enable_irq();
} else {
uint32_t _pri = pri & cm3_irq_pri_mask;
if (_pri == 0)
__set_BASEPRI(1 << (8 - cm3_num_irq_pri_bits));
else
__set_BASEPRI(_pri);
__enable_irq(); // cpsid i
}
}