[rpi3]64bit platform support

arch/arm/arm/mp.c

@@ -33,6 +33,8 @@
 #elif PLATFORM_BCM2835
 /* bcm2835 has a weird custom interrupt controller for MP */
 extern void bcm2835_send_ipi(uint irq, uint cpu_mask);
+#elif PLATFORM_BCM2837
+extern void bcm2835_send_ipi(uint irq, uint cpu_mask);
 #else
 #error need other implementation of interrupt controller that can ipi
 #endif

arch/arm64/asm.S

@@ -83,5 +83,60 @@ FUNCTION(arm64_el3_to_el1)
 
     eret
 
+FUNCTION(arm64_elX_to_el1)
+    mrs x0, CurrentEL
+
+    cmp x0, #(0b01 << 2)
+    bne .notEL1
+    /* Already in EL1 */
+    ret 
+
+.notEL1:
+    cmp x0, #(0b10 << 2)
+    beq .inEL2
+
+
+    /* set EL2 to 64bit */
+    mrs x0, scr_el3
+    orr x0, x0, #(1<<10)
+    msr scr_el3, x0
+
+
+    adr x0, .Ltarget
+    msr elr_el3, x0
+
+    mov x0, #((0b1111 << 6) | (0b0101)) /* EL1h runlevel */
+    msr spsr_el3, x0
+    b   .confEL1
+
+.inEL2:
+    adr x0, .Ltarget
+    msr elr_el2, x0
+    mov x0, #((0b1111 << 6) | (0b0101)) /* EL1h runlevel */
+    msr spsr_el2, x0
+   
+
+
+.confEL1:
+    /* disable EL2 coprocessor traps */
+    mov x0, #0x33ff
+    msr cptr_el2, x0
+
+    /* set EL1 to 64bit */
+    mov x0, #(1<<31)
+    msr hcr_el2, x0
+
+    /* disable EL1 FPU traps */
+    mov x0, #(0b11<<20)
+    msr cpacr_el1, x0
+
+    /* set up the EL1 bounce interrupt */
+    mov x0, sp
+    msr sp_el1, x0
+
+    isb
+    eret
+
+
 .Ltarget:
     ret

arch/arm64/mp.c

@@ -30,8 +30,8 @@
 
 #if WITH_DEV_INTERRUPT_ARM_GIC
 #include <dev/interrupt/arm_gic.h>
-#else
-#error need other implementation of interrupt controller that can ipi
+//#else
+//#error need other implementation of interrupt controller that can ipi
 #endif
 
 #define LOCAL_TRACE 0

arch/arm64/start.S

@@ -30,7 +30,13 @@ attr                    .req x27
 
 .section .text.boot
 FUNCTION(_start)
+.globl arm_reset
+arm_reset:
+
 #if WITH_KERNEL_VM
+
+    bl      arm64_elX_to_el1
+
     /* enable caches so atomics and spinlocks work */
     mrs     tmp, sctlr_el1
     orr     tmp, tmp, #(1<<12) /* Enable icache */