diff --git a/platform/stm32f7xx/include/platform/sdram.h b/platform/stm32f7xx/include/platform/sdram.h new file mode 100644 index 00000000..00788f4a --- /dev/null +++ b/platform/stm32f7xx/include/platform/sdram.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2015 Carlos Pizano-Uribe + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files + * (the "Software"), to deal in the Software without restriction, + * including without limitation the rights to use, copy, modify, merge, + * publish, distribute, sublicense, and/or sell copies of the Software, + * and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#pragma once + +#include + +enum sdram_bus_width { + SDRAM_BUS_WIDTH_8, + SDRAM_BUS_WIDTH_16, + SDRAM_BUS_WIDTH_32 +}; + +enum sdram_cas_latency { + SDRAM_CAS_LATENCY_1, + SDRAM_CAS_LATENCY_2, + SDRAM_CAS_LATENCY_3 +}; + +enum sdram_col_bits_num { + SDRAM_COLUMN_BITS_8, + SDRAM_COLUMN_BITS_9, + SDRAM_COLUMN_BITS_10, + SDRAM_COLUMN_BITS_11 +}; + +typedef struct _sdram_config { + enum sdram_bus_width bus_width; + enum sdram_cas_latency cas_latency; + enum sdram_col_bits_num col_bits_num; +} sdram_config_t; + +// Left to each target to define the GPIO to DRAM bus mapping. +void stm_sdram_GPIO_init(void); + +uint8_t stm32_sdram_init(sdram_config_t* config); + diff --git a/platform/stm32f7xx/rules.mk b/platform/stm32f7xx/rules.mk index 8bed267d..4cbe5520 100644 --- a/platform/stm32f7xx/rules.mk +++ b/platform/stm32f7xx/rules.mk @@ -38,6 +38,7 @@ MODULE_SRCS += \ $(LOCAL_DIR)/timer.c \ $(LOCAL_DIR)/uart.c \ $(LOCAL_DIR)/vectab.c \ + $(LOCAL_DIR)/sdram.c \ # use a two segment memory layout, where all of the read-only sections # of the binary reside in rom, and the read/write are in memory. The diff --git a/target/stm32746g-eval2/sdram.c b/platform/stm32f7xx/sdram.c similarity index 71% rename from target/stm32746g-eval2/sdram.c rename to platform/stm32f7xx/sdram.c index 1278b1d1..9324c16f 100644 --- a/target/stm32746g-eval2/sdram.c +++ b/platform/stm32f7xx/sdram.c @@ -55,10 +55,11 @@ #include #include #include +#include /* * sdram initialization sequence, taken from - * STM32Cube_FW_F7_V1.1.0/Drivers/BSP/STM32756G_EVAL/stm32756g_eval_sdram.[ch] + * STM32Cube_FW_F7_V1.1.0/Drivers/BSP */ /** @@ -67,22 +68,10 @@ #define SDRAM_OK ((uint8_t)0x00) #define SDRAM_ERROR ((uint8_t)0x01) -/** @defgroup STM32756G_EVAL_SDRAM_Exported_Constants - * @{ - */ -#define SDRAM_DEVICE_ADDR ((uint32_t)0xC0000000) -#define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */ +/* SDRAM refresh counter (100Mhz SD clock) */ +#define REFRESH_COUNT ((uint32_t)0x0603) -/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */ -/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 */ -#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_32 - -#define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 -/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */ - -#define REFRESH_COUNT ((uint32_t)0x0603) /* SDRAM refresh counter (100Mhz SD clock) */ - -#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) +#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) /* DMA definitions for SDRAM DMA transfer */ #define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE @@ -91,9 +80,6 @@ #define SDRAM_DMAx_STREAM DMA2_Stream0 #define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn #define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler -/** - * @} - */ /** * @brief FMC SDRAM Mode definition register defines @@ -104,6 +90,7 @@ #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_1 ((uint16_t)0x0010) #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) @@ -112,111 +99,13 @@ static SDRAM_HandleTypeDef sdramHandle; -/** - * @brief Initializes SDRAM MSP. - * @param hsdram: SDRAM handle - * @retval None - */ -static void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) -{ - static DMA_HandleTypeDef dma_handle; - GPIO_InitTypeDef gpio_init_structure; - - /* Enable FMC clock */ - __HAL_RCC_FMC_CLK_ENABLE(); - - /* Enable chosen DMAx clock */ - __DMAx_CLK_ENABLE(); - - /* Enable GPIOs clock */ - __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOI_CLK_ENABLE(); - - /* Common GPIO configuration */ - gpio_init_structure.Mode = GPIO_MODE_AF_PP; - gpio_init_structure.Pull = GPIO_PULLUP; - gpio_init_structure.Speed = GPIO_SPEED_FAST; - gpio_init_structure.Alternate = GPIO_AF12_FMC; - - /* GPIOD configuration */ - gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\ - GPIO_PIN_14 | GPIO_PIN_15; - - - HAL_GPIO_Init(GPIOD, &gpio_init_structure); - - /* GPIOE configuration */ - gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ - GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ - GPIO_PIN_15; - - HAL_GPIO_Init(GPIOE, &gpio_init_structure); - - /* GPIOF configuration */ - gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ - GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ - GPIO_PIN_15; - - HAL_GPIO_Init(GPIOF, &gpio_init_structure); - - /* GPIOG configuration */ - gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ - GPIO_PIN_15; - HAL_GPIO_Init(GPIOG, &gpio_init_structure); - - /* GPIOH configuration */ - gpio_init_structure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_9 |\ - GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ - GPIO_PIN_15; - HAL_GPIO_Init(GPIOH, &gpio_init_structure); - - /* GPIOI configuration */ - gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\ - GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10; - HAL_GPIO_Init(GPIOI, &gpio_init_structure); - - /* Configure common DMA parameters */ - dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; - dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; - dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; - dma_handle.Init.MemInc = DMA_MINC_ENABLE; - dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; - dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; - dma_handle.Init.Mode = DMA_NORMAL; - dma_handle.Init.Priority = DMA_PRIORITY_HIGH; - dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; - dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; - - dma_handle.Instance = SDRAM_DMAx_STREAM; - - /* Associate the DMA handle */ - __HAL_LINKDMA(hsdram, hdma, dma_handle); - - /* Deinitialize the stream for new transfer */ - HAL_DMA_DeInit(&dma_handle); - - /* Configure the DMA stream */ - HAL_DMA_Init(&dma_handle); - -#if 0 - /* NVIC configuration for DMA transfer complete interrupt */ - HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); -#endif -} - /** * @brief Programs the SDRAM device. * @param RefreshCount: SDRAM refresh counter value * @retval None */ -static void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) +static void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount, + uint32_t CasLatency) { __IO uint32_t tmpmrd = 0; FMC_SDRAM_CommandTypeDef Command; @@ -254,10 +143,11 @@ static void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) /* Step 5: Program the external memory mode register */ tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\ SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\ - SDRAM_MODEREG_CAS_LATENCY_3 |\ SDRAM_MODEREG_OPERATING_MODE_STANDARD |\ SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + tmpmrd |= CasLatency; + Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1; Command.AutoRefreshNumber = 1; @@ -271,13 +161,55 @@ static void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount) HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount); } +static uint32_t GetMemoryWidth(sdram_config_t* config) +{ + switch (config->bus_width) { + case SDRAM_BUS_WIDTH_8 : return FMC_SDRAM_MEM_BUS_WIDTH_8; + case SDRAM_BUS_WIDTH_16 : return FMC_SDRAM_MEM_BUS_WIDTH_16; + case SDRAM_BUS_WIDTH_32 : return FMC_SDRAM_MEM_BUS_WIDTH_32; + } + return 0; +} + +static uint32_t GetColumnBitsNumber(sdram_config_t* config) +{ + switch (config->col_bits_num) { + case SDRAM_COLUMN_BITS_8 : return FMC_SDRAM_COLUMN_BITS_NUM_8; + case SDRAM_COLUMN_BITS_9 : return FMC_SDRAM_COLUMN_BITS_NUM_9; + case SDRAM_COLUMN_BITS_10 : return FMC_SDRAM_COLUMN_BITS_NUM_10; + case SDRAM_COLUMN_BITS_11 : return FMC_SDRAM_COLUMN_BITS_NUM_11; + } + return 0; +} + +static uint32_t GetCasLatencyFMC(sdram_config_t* config) +{ + switch (config->cas_latency) { + case SDRAM_CAS_LATENCY_1 : return FMC_SDRAM_CAS_LATENCY_1; + case SDRAM_CAS_LATENCY_2 : return FMC_SDRAM_CAS_LATENCY_2; + case SDRAM_CAS_LATENCY_3 : return FMC_SDRAM_CAS_LATENCY_3; + } + return 0; +} + +static uint32_t GetCasLatencyModeReg(sdram_config_t* config) +{ + switch (config->cas_latency) { + case SDRAM_CAS_LATENCY_1 : return SDRAM_MODEREG_CAS_LATENCY_1; + case SDRAM_CAS_LATENCY_2 : return SDRAM_MODEREG_CAS_LATENCY_2; + case SDRAM_CAS_LATENCY_3 : return SDRAM_MODEREG_CAS_LATENCY_3; + } + return 0; +} + /** * @brief Initializes the SDRAM device. * @retval SDRAM status */ -uint8_t BSP_SDRAM_Init(void) +uint8_t stm32_sdram_init(sdram_config_t* config) { static uint8_t sdramstatus = SDRAM_ERROR; + static DMA_HandleTypeDef dma_handle; /* SDRAM device configuration */ sdramHandle.Instance = FMC_SDRAM_DEVICE; @@ -293,18 +225,55 @@ uint8_t BSP_SDRAM_Init(void) Timing.RCDDelay = 2; sdramHandle.Init.SDBank = FMC_SDRAM_BANK1; - sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9; + sdramHandle.Init.ColumnBitsNumber = GetColumnBitsNumber(config); sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; - sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; + sdramHandle.Init.MemoryDataWidth = GetMemoryWidth(config); sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; - sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3; + sdramHandle.Init.CASLatency = GetCasLatencyFMC(config); sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; - sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD; + sdramHandle.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2; sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE; sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0; - /* SDRAM controller initialization */ - BSP_SDRAM_MspInit(&sdramHandle); + /* Enable FMC clock */ + __HAL_RCC_FMC_CLK_ENABLE(); + + /* Enable chosen DMAx clock */ + __DMAx_CLK_ENABLE(); + + /* SDRAM GPIO initialization */ + stm_sdram_GPIO_init(); + + /* Configure common DMA parameters */ + dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL; + dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY; + dma_handle.Init.PeriphInc = DMA_PINC_ENABLE; + dma_handle.Init.MemInc = DMA_MINC_ENABLE; + dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + dma_handle.Init.Mode = DMA_NORMAL; + dma_handle.Init.Priority = DMA_PRIORITY_HIGH; + dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + dma_handle.Init.MemBurst = DMA_MBURST_SINGLE; + dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE; + + dma_handle.Instance = SDRAM_DMAx_STREAM; + + /* Associate the DMA handle */ + __HAL_LINKDMA(&sdramHandle, hdma, dma_handle); + + /* Deinitialize the stream for new transfer */ + HAL_DMA_DeInit(&dma_handle); + + /* Configure the DMA stream */ + HAL_DMA_Init(&dma_handle); + +#if 0 + /* NVIC configuration for DMA transfer complete interrupt */ + HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn); +#endif if (HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK) { sdramstatus = SDRAM_ERROR; @@ -313,7 +282,8 @@ uint8_t BSP_SDRAM_Init(void) } /* SDRAM initialization sequence */ - BSP_SDRAM_Initialization_sequence(REFRESH_COUNT); + BSP_SDRAM_Initialization_sequence(REFRESH_COUNT, + GetCasLatencyModeReg(config)); return sdramstatus; } diff --git a/target/stm32746g-eval2/init.c b/target/stm32746g-eval2/init.c index 3d5562a2..ecf11717 100644 --- a/target/stm32746g-eval2/init.c +++ b/target/stm32746g-eval2/init.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -38,7 +39,6 @@ #include #endif -extern uint8_t BSP_SDRAM_Init(void); extern uint8_t BSP_LCD_Init(void); extern uint8_t BSP_SRAM_Init(void); @@ -57,8 +57,14 @@ void target_early_init(void) /* now that the uart gpios are configured, enable the debug uart */ stm32_debug_early_init(); +#if defined(ENABLE_SDRAM) /* initialize sdram */ - BSP_SDRAM_Init(); + sdram_config_t sdram_config; + sdram_config.bus_width = SDRAM_BUS_WIDTH_32; + sdram_config.cas_latency = SDRAM_CAS_LATENCY_3; + sdram_config.col_bits_num = SDRAM_COLUMN_BITS_9; + stm32_sdram_init(&sdram_config); +#endif /* initialize external sram */ BSP_SRAM_Init(); @@ -322,5 +328,60 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) */ } +/** + * @brief Initializes SDRAM GPIO. + * @retval None + */ +/* called back from BSP_SDRAM_Init */ +void stm_sdram_GPIO_init(void) +{ + GPIO_InitTypeDef gpio_init_structure; + /* Enable GPIOs clock */ + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOI_CLK_ENABLE(); + + /* Common GPIO configuration */ + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Pull = GPIO_PULLUP; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + gpio_init_structure.Alternate = GPIO_AF12_FMC; + + /* GPIOD configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\ + GPIO_PIN_14 | GPIO_PIN_15; + HAL_GPIO_Init(GPIOD, &gpio_init_structure); + + /* GPIOE configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOE, &gpio_init_structure); + + /* GPIOF configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ + GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOF, &gpio_init_structure); + + /* GPIOG configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOG, &gpio_init_structure); + + /* GPIOH configuration */ + gpio_init_structure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_9 |\ + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOH, &gpio_init_structure); + + /* GPIOI configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\ + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10; + HAL_GPIO_Init(GPIOI, &gpio_init_structure); +} diff --git a/target/stm32746g-eval2/rules.mk b/target/stm32746g-eval2/rules.mk index b23b2d0d..739118b6 100644 --- a/target/stm32746g-eval2/rules.mk +++ b/target/stm32746g-eval2/rules.mk @@ -40,7 +40,6 @@ GLOBAL_INCLUDES += $(LOCAL_DIR)/include MODULE_SRCS += \ $(LOCAL_DIR)/init.c \ $(LOCAL_DIR)/lcd.c \ - $(LOCAL_DIR)/sdram.c \ $(LOCAL_DIR)/sram.c MODULE_DEPS += \ diff --git a/target/stm32f746g-disco/init.c b/target/stm32f746g-disco/init.c index 3d21c791..99cc66fb 100644 --- a/target/stm32f746g-disco/init.c +++ b/target/stm32f746g-disco/init.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -44,6 +45,15 @@ void target_early_init(void) /* now that the uart gpios are configured, enable the debug uart */ stm32_debug_early_init(); + +#if defined(ENABLE_SDRAM) + /* initialize sdram */ + sdram_config_t sdram_config; + sdram_config.bus_width = SDRAM_BUS_WIDTH_16; + sdram_config.cas_latency = SDRAM_CAS_LATENCY_2; + sdram_config.col_bits_num = SDRAM_COLUMN_BITS_8; + stm32_sdram_init(&sdram_config); +#endif } void target_init(void) @@ -51,3 +61,58 @@ void target_init(void) stm32_debug_init(); } + +/** + * @brief Initializes SDRAM GPIO. + * @retval None + */ +/* called back from stm32_sdram_init */ +void stm_sdram_GPIO_init(void) +{ + GPIO_InitTypeDef gpio_init_structure; + + /* Enable GPIOs clock */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOE_CLK_ENABLE(); + __HAL_RCC_GPIOF_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + + /* Common GPIO configuration */ + gpio_init_structure.Mode = GPIO_MODE_AF_PP; + gpio_init_structure.Pull = GPIO_PULLUP; + gpio_init_structure.Speed = GPIO_SPEED_FAST; + gpio_init_structure.Alternate = GPIO_AF12_FMC; + + /* GPIOC configuration */ + gpio_init_structure.Pin = GPIO_PIN_3; + HAL_GPIO_Init(GPIOC, &gpio_init_structure); + + /* GPIOD configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\ + GPIO_PIN_14 | GPIO_PIN_15; + HAL_GPIO_Init(GPIOD, &gpio_init_structure); + + /* GPIOE configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\ + GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOE, &gpio_init_structure); + + /* GPIOF configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\ + GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOF, &gpio_init_structure); + + /* GPIOG configuration */ + gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\ + GPIO_PIN_15; + HAL_GPIO_Init(GPIOG, &gpio_init_structure); + + /* GPIOH configuration */ + gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5; + HAL_GPIO_Init(GPIOH, &gpio_init_structure); +} +