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[platform] move alterasoc and zynq timer to the shared generic cortex a9 driver

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This commit is contained in:
Travis Geiselbrecht
2014-05-11 00:45:58 -07:00
parent 1b08f503e9
commit 036647ec1d
8 changed files with 11 additions and 307 deletions
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3
platform/alterasoc/include/platform/alterasoc.h
View File

@@ -86,9 +86,6 @@
#define GIC_DISTRIB_BASE (CPUPRIV_BASE + 0x1000)
/* interrupts */
#define CPU_GLOB_TIMER 27 // cortex-a9 specific timers
#define CPU_PRIV_TIMER 29
#define CPU_WATCHDOG 30
#define FPGA_INT(n) (72 + (n))

4
platform/alterasoc/platform.c
View File

@@ -27,7 +27,9 @@
#include <arch/arm/mmu.h>
#include <dev/uart.h>
#include <dev/interrupt/arm_gic.h>
#include <dev/timer/arm_cortex_a9.h>
#include <platform.h>
#include <platform/alterasoc.h>
#include "platform_p.h"
void platform_init_mmu_mappings(void)
@@ -50,7 +52,7 @@ void platform_early_init(void)
arm_gic_init();
/* initialize the timer block */
platform_init_timer(TIMER_CLOCK_FREQ);
arm_cortex_a9_timer_init(CPUPRIV_BASE, TIMER_CLOCK_FREQ);
}
void platform_init(void)

4
platform/alterasoc/rules.mk
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@@ -7,7 +7,8 @@ ARM_CPU := cortex-a9
MODULE_DEPS := \
lib/cbuf \
dev/interrupt/arm_gic
dev/interrupt/arm_gic \
dev/timer/arm_cortex_a9
GLOBAL_INCLUDES += \
$(LOCAL_DIR)/include
@@ -16,7 +17,6 @@ MODULE_SRCS += \
$(LOCAL_DIR)/clocks.c \
$(LOCAL_DIR)/debug.c \
$(LOCAL_DIR)/platform.c \
$(LOCAL_DIR)/timer.c \
$(LOCAL_DIR)/uart.c
MEMBASE := 0x0

150
platform/alterasoc/timer.c
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@@ -1,150 +0,0 @@
/*
* Copyright (c) 2014 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include <debug.h>
#include <sys/types.h>
#include <err.h>
#include <stdio.h>
#include <assert.h>
#include <trace.h>
#include <kernel/thread.h>
#include <platform.h>
#include <platform/interrupts.h>
#include <platform/timer.h>
#include <platform/alterasoc.h>
#include "platform_p.h"
/* driver for cortex-a9's private timer */
#define LOCAL_TRACE 0
#define TIMREG(reg) (*REG32(PRIV_TIMER_BASE + (reg)))
#define TIMER_LOAD (0x00)
#define TIMER_COUNTER (0x04)
#define TIMER_CONTROL (0x08)
#define TIMER_ISR (0x0c)
#define WDOG_LOAD (0x20)
#define WDOG_COUNTER (0x24)
#define WDOG_CONTROL (0x28)
#define WDOG_ISR (0x2c)
#define GTIMREG(reg) (*REG32(GLOBAL_TIMER_BASE + (reg)))
#define GTIMER_COUNT_LO (0x00)
#define GTIMER_COUNT_HI (0x04)
#define GTIMER_CONTROL (0x08)
#define GTIMER_ISR (0x0c)
#define GTIMER_COMPARE_LO (0x10)
#define GTIMER_COMPARE_HI (0x14)
#define GTIMER_INCREMENT (0x18)
static platform_timer_callback t_callback;
static volatile uint ticks = 0;
static lk_time_t periodic_interval;
static uint32_t timer_freq;
uint64_t get_global_val(void)
{
uint32_t lo, hi;
retry:
hi = GTIMREG(GTIMER_COUNT_HI);
lo = GTIMREG(GTIMER_COUNT_LO);
if (GTIMREG(GTIMER_COUNT_HI) != hi)
goto retry;
return ((uint64_t)hi << 32 | lo);
}
status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval)
{
enter_critical_section();
LTRACEF("callback %p, arg %p, interval %lu\n", callback, arg, interval);
t_callback = callback;
periodic_interval = interval;
// disable timer
TIMREG(TIMER_CONTROL) = 0;
TIMREG(TIMER_LOAD) = (((uint64_t)timer_freq * interval) / 1000);
TIMREG(TIMER_CONTROL) = (1<<2) | (1<<1) | (1<<0); // irq enable, autoreload, enable
unmask_interrupt(CPU_PRIV_TIMER);
exit_critical_section();
return NO_ERROR;
}
lk_bigtime_t current_time_hires(void)
{
lk_bigtime_t time;
time = ticks * periodic_interval * 1000ULL;
return time;
}
lk_time_t current_time(void)
{
lk_time_t time;
time = ticks * periodic_interval;
return time;
}
static enum handler_return platform_tick(void *arg)
{
ticks++;
LTRACE;
TIMREG(TIMER_ISR) = 1; // ack the irq
if (t_callback) {
return t_callback(arg, current_time());
} else {
return INT_NO_RESCHEDULE;
}
}
void platform_init_timer(uint32_t freq)
{
/* disable timer */
TIMREG(TIMER_CONTROL) = 0;
/* kill the watchdog */
TIMREG(WDOG_CONTROL) = 0;
/* save the timer frequency for later calculations */
timer_freq = freq;
register_int_handler(CPU_PRIV_TIMER, &platform_tick, NULL);
}
/* vim: set ts=4 sw=4 expandtab: */

3
platform/zynq/include/platform/zynq.h
View File

@@ -66,9 +66,6 @@
#define L2CACHE_BASE (CPUPRIV_BASE + 0x2000)
/* interrupts */
#define CPU_GLOB_TIMER 27 // cortex-a9 specific timers
#define CPU_PRIV_TIMER 29
#define CPU_WATCHDOG 30
#define TTC0_A_INT 42
#define TTC0_B_INT 43
#define TTC0_C_INT 44

3
platform/zynq/platform.c
View File

@@ -25,6 +25,7 @@
#include <arch/arm/mmu.h>
#include <dev/uart.h>
#include <dev/interrupt/arm_gic.h>
#include <dev/timer/arm_cortex_a9.h>
#include <platform.h>
#include <platform/zynq.h>
#include "platform_p.h"
@@ -47,7 +48,7 @@ void platform_early_init(void)
arm_gic_init();
/* initialize the timer block */
platform_init_timer(TIMER_CLOCK_FREQ);
arm_cortex_a9_timer_init(CPUPRIV_BASE, TIMER_CLOCK_FREQ);
}
void platform_init(void)

7
platform/zynq/rules.mk
View File

@@ -7,7 +7,8 @@ ARM_CPU := cortex-a9
MODULE_DEPS := \
lib/cbuf \
dev/interrupt/arm_gic
dev/interrupt/arm_gic \
dev/timer/arm_cortex_a9
GLOBAL_INCLUDES += \
$(LOCAL_DIR)/include
@@ -16,7 +17,6 @@ MODULE_SRCS += \
$(LOCAL_DIR)/clocks.c \
$(LOCAL_DIR)/debug.c \
$(LOCAL_DIR)/platform.c \
$(LOCAL_DIR)/timer.c \
$(LOCAL_DIR)/uart.c
ifeq ($(ZYNQ_USE_SRAM),1)
@@ -29,8 +29,7 @@ endif
GLOBAL_DEFINES += \
MEMBASE=$(MEMBASE) \
MEMSIZE=$(MEMSIZE) \
PLATFORM_HAS_DYNAMIC_TIMER=1
MEMSIZE=$(MEMSIZE)
LINKER_SCRIPT += \
$(BUILDDIR)/system-onesegment.ld

144
platform/zynq/timer.c
View File

@@ -33,149 +33,7 @@
#include <platform/zynq.h>
#include "platform_p.h"
/* driver for cortex-a9's private timer */
#define LOCAL_TRACE 0
#define TIMREG(reg) (*REG32(PRIV_TIMER_BASE + (reg)))
#define TIMER_LOAD (0x00)
#define TIMER_COUNTER (0x04)
#define TIMER_CONTROL (0x08)
#define TIMER_ISR (0x0c)
#define WDOG_LOAD (0x20)
#define WDOG_COUNTER (0x24)
#define WDOG_CONTROL (0x28)
#define WDOG_ISR (0x2c)
#define GTIMREG(reg) (*REG32(GLOBAL_TIMER_BASE + (reg)))
#define GTIMER_COUNT_LO (0x00)
#define GTIMER_COUNT_HI (0x04)
#define GTIMER_CONTROL (0x08)
#define GTIMER_ISR (0x0c)
#define GTIMER_COMPARE_LO (0x10)
#define GTIMER_COMPARE_HI (0x14)
#define GTIMER_INCREMENT (0x18)
static platform_timer_callback t_callback;
static lk_time_t periodic_interval;
static lk_time_t oneshot_interval;
static uint32_t timer_freq;
static uint32_t timer_freq_usec_conversion;
static uint32_t timer_freq_msec_conversion;
uint64_t get_global_val(void)
{
uint32_t lo, hi;
retry:
hi = GTIMREG(GTIMER_COUNT_HI);
lo = GTIMREG(GTIMER_COUNT_LO);
if (GTIMREG(GTIMER_COUNT_HI) != hi)
goto retry;
return ((uint64_t)hi << 32 | lo);
}
lk_bigtime_t current_time_hires(void)
{
lk_bigtime_t time;
time = get_global_val() / timer_freq_usec_conversion;
return time;
}
lk_time_t current_time(void)
{
lk_time_t time;
time = get_global_val() / timer_freq_msec_conversion;
return time;
}
status_t platform_set_periodic_timer(platform_timer_callback callback, void *arg, lk_time_t interval)
{
LTRACEF("callback %p, arg %p, interval %lu\n", callback, arg, interval);
enter_critical_section();
t_callback = callback;
periodic_interval = interval;
// disable timer
TIMREG(TIMER_CONTROL) = 0;
TIMREG(TIMER_LOAD) = ((uint64_t)timer_freq_msec_conversion * interval);
TIMREG(TIMER_CONTROL) = (1<<2) | (1<<1) | (1<<0); // irq enable, autoreload, enable
unmask_interrupt(CPU_PRIV_TIMER);
exit_critical_section();
return NO_ERROR;
}
status_t platform_set_oneshot_timer (platform_timer_callback callback, void *arg, lk_time_t interval)
{
LTRACEF("callback %p, arg %p, timeout %lu\n", callback, arg, interval);
enter_critical_section();
t_callback = callback;
oneshot_interval = interval;
// disable timer
TIMREG(TIMER_CONTROL) = 0;
TIMREG(TIMER_LOAD) = ((uint64_t)timer_freq_msec_conversion * interval);
TIMREG(TIMER_CONTROL) = (1<<2) | (1<<0) | (1<<0); // irq enable, oneshot, enable
unmask_interrupt(CPU_PRIV_TIMER);
exit_critical_section();
return NO_ERROR;
}
void platform_stop_timer(void)
{
LTRACE;
}
static enum handler_return platform_tick(void *arg)
{
LTRACE;
TIMREG(TIMER_ISR) = 1; // ack the irq
if (t_callback) {
return t_callback(arg, current_time());
} else {
return INT_NO_RESCHEDULE;
}
}
void platform_init_timer(uint32_t freq)
{
/* disable timer */
TIMREG(TIMER_CONTROL) = 0;
/* kill the watchdog */
TIMREG(WDOG_CONTROL) = 0;
/* save the timer frequency for later calculations */
timer_freq = freq;
/* precompute the conversion factor for global time to real time */
timer_freq_usec_conversion = timer_freq / 1000000UL;
timer_freq_msec_conversion = timer_freq / 1000UL;
register_int_handler(CPU_PRIV_TIMER, &platform_tick, NULL);
}
/* unused, arm_cortex_a9_timer does timer duty */
#if 0
/* driver for Cadence triple timer counter (TTC) */