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lk/arch/riscv/start.S

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[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
2018-10-14 17:12:01 -07:00
/*
* Copyright (c) 2015 Travis Geiselbrecht
*
[license] replace the longer full MIT license with a shorter one Used scripts/replacelic. Everything seems to build fine.
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* Use of this source code is governed by a MIT-style
* license that can be found in the LICENSE file or at
* https://opensource.org/licenses/MIT
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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*/
[include][lk] fixup lk/ include path move
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#include <lk/asm.h>
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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.section ".text.boot"
FUNCTION(_start)
[arch][riscv] set up the global pointer register The linker will automatically relax any dereferences and calculations for symbols located near the symbol __global_pointer$.
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.option push
.option norelax
# set the global pointer
la gp, __global_pointer$
.option pop
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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# set the default stack
la sp, default_stack_top
[arch][riscv] port to riscv64 Very little needed to port except to conditionalize some assembly in the context switch and exception code. Mostly needed to move build system stuff around and add a new project.
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#if ARCH_RISCV_TWOSEGMENT
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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# copy preinitialized data from flash to memory
la t0, __data_start_rom
la t1, __data_start
la t2, __data_end
beq t0, t1, 1f
0:
lw t3, (t0)
sw t3, (t1)
add t0, t0, 4
add t1, t1, 4
bne t1, t2, 0b
#endif
# zero bss
1:
la t0, __bss_start
la t1, __bss_end
0:
sw x0, (t0)
add t0, t0, 4
bne t0, t1, 0b
# call main
jal lk_main
[arch][riscv32] rename the qemu target sifive-e The initial port is really a Sifive E platform. Call it what it is and make space for bringing up the Sifive U and virt qemu target.
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# should never return here
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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j .
.bss
.align 4
LOCAL_DATA(default_stack)
.skip 1024
LOCAL_DATA(default_stack_top)
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