lk/project/qemu-riscv32-test.mk

include project/target/qemu-riscv32.mk
include project/virtual/test.mk
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place. 2018-10-14 17:12:01 -07:00			`include project/target/qemu-riscv32.mk`
			`include project/virtual/test.mk`