lk/target/sifive-unleashed/rules.mk

LOCAL_DIR := $(GET_LOCAL_DIR)
MODULE := $(LOCAL_DIR)

PLATFORM := sifive
VARIANT := sifive_u

WITH_SMP := 1
BOOT_HART := 1

GLOBAL_DEFINES += SIFIVE_FREQ=500000000 # 500 MHz

RISCV_MODE ?= machine

ifeq ($(RISCV_MODE),supervisor)
MEMBASE ?= 0x080200000
SMP_MAX_CPUS := 4
else
MEMBASE ?= 0x080000000
SMP_MAX_CPUS := 5
endif
MEMSIZE ?= 0x200000000 # 8 GiB

MODULE_SRCS := $(LOCAL_DIR)/target.c
# set some global defines based on capability
GLOBAL_DEFINES += TARGET_HAS_DEBUG_LED=1
GLOBAL_DEFINES += PLATFORM_HAS_DYNAMIC_TIMER=1
GLOBAL_DEFINES += ARCH_RISCV_CLINT_BASE=0x02000000
GLOBAL_DEFINES += ARCH_RISCV_MTIME_RATE=1000000  # 1 MHz

include make/module.mk
[arch][riscv] Add basic support for SiFive HiFive Unleashed Most of changes were moving around where macros were defined, plus the following: - Remove requirement for floating point on RV64 to support booting monitor core on U54 SoC. - Add support for Debug LEDs on HiFive Unleashed Board 2019-12-03 15:48:18 -08:00			`LOCAL_DIR := $(GET_LOCAL_DIR)`
			`MODULE := $(LOCAL_DIR)`

			`PLATFORM := sifive`
			`VARIANT := sifive_u`

[arch][riscv] Expose RISC-V mp kernel start Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation 2019-12-04 09:08:57 -08:00			`WITH_SMP := 1`
[arch][riscv] Add support for running in supervisor mode Add support for running LK in supervisor mode or machine mode. - Macro-ify CSR access to use correct CSR # or use SBI call as req'd - Add support to make SBI calls - Split CLINT and lk timer abstraction so that RISC-V timer can use SBI as required. - Add support for booting other harts as primary since hart0 on U540 does not support S-mode. A map is used to get LK cpu number from hartid. 2019-12-04 09:35:56 -08:00			`BOOT_HART := 1`
[arch][riscv] Expose RISC-V mp kernel start Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation 2019-12-04 09:08:57 -08:00
[arch][riscv] Add basic support for SiFive HiFive Unleashed Most of changes were moving around where macros were defined, plus the following: - Remove requirement for floating point on RV64 to support booting monitor core on U54 SoC. - Add support for Debug LEDs on HiFive Unleashed Board 2019-12-03 15:48:18 -08:00			`GLOBAL_DEFINES += SIFIVE_FREQ=500000000 # 500 MHz`

[arch][riscv] Add support for running in supervisor mode Add support for running LK in supervisor mode or machine mode. - Macro-ify CSR access to use correct CSR # or use SBI call as req'd - Add support to make SBI calls - Split CLINT and lk timer abstraction so that RISC-V timer can use SBI as required. - Add support for booting other harts as primary since hart0 on U540 does not support S-mode. A map is used to get LK cpu number from hartid. 2019-12-04 09:35:56 -08:00			`RISCV_MODE ?= machine`

			`ifeq ($(RISCV_MODE),supervisor)`
			`MEMBASE ?= 0x080200000`
			`SMP_MAX_CPUS := 4`
			`else`
[arch][riscv] Add basic support for SiFive HiFive Unleashed Most of changes were moving around where macros were defined, plus the following: - Remove requirement for floating point on RV64 to support booting monitor core on U54 SoC. - Add support for Debug LEDs on HiFive Unleashed Board 2019-12-03 15:48:18 -08:00			`MEMBASE ?= 0x080000000`
[arch][riscv] Add support for running in supervisor mode Add support for running LK in supervisor mode or machine mode. - Macro-ify CSR access to use correct CSR # or use SBI call as req'd - Add support to make SBI calls - Split CLINT and lk timer abstraction so that RISC-V timer can use SBI as required. - Add support for booting other harts as primary since hart0 on U540 does not support S-mode. A map is used to get LK cpu number from hartid. 2019-12-04 09:35:56 -08:00			`SMP_MAX_CPUS := 5`
			`endif`
[arch][riscv] Add basic support for SiFive HiFive Unleashed Most of changes were moving around where macros were defined, plus the following: - Remove requirement for floating point on RV64 to support booting monitor core on U54 SoC. - Add support for Debug LEDs on HiFive Unleashed Board 2019-12-03 15:48:18 -08:00			`MEMSIZE ?= 0x200000000 # 8 GiB`

			`MODULE_SRCS := $(LOCAL_DIR)/target.c`
			`# set some global defines based on capability`
			`GLOBAL_DEFINES += TARGET_HAS_DEBUG_LED=1`
			`GLOBAL_DEFINES += PLATFORM_HAS_DYNAMIC_TIMER=1`
			`GLOBAL_DEFINES += ARCH_RISCV_CLINT_BASE=0x02000000`
			`GLOBAL_DEFINES += ARCH_RISCV_MTIME_RATE=1000000 # 1 MHz`

			`include make/module.mk`