lk/platform/sifive/rules.mk

LOCAL_DIR := $(GET_LOCAL_DIR)

MODULE := $(LOCAL_DIR)

ARCH := riscv
SUBARCH ?= 32
VARIANT ?= sifive_e

MODULE_DEPS += lib/cbuf

MODULE_SRCS += $(LOCAL_DIR)/platform.c
MODULE_SRCS += $(LOCAL_DIR)/plic.c
MODULE_SRCS += $(LOCAL_DIR)/uart.c

ROMBASE ?= 0x20400000 # if running from rom, start here
MEMBASE ?= 0x80000000
MEMSIZE ?= 0x00100000 # default to 1MB

ifeq ($(VARIANT),sifive_e)
# uses a two segment layout, select the appropriate linker script
ARCH_RISCV_TWOSEGMENT := 1
# sets a few options in the riscv arch
ARCH_RISCV_EMBEDDED := 1
endif

# sifive_e or _u?
GLOBAL_DEFINES += PLATFORM_${VARIANT}=1

include make/module.mk
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place. 2018-10-14 17:12:01 -07:00			`LOCAL_DIR := $(GET_LOCAL_DIR)`

			`MODULE := $(LOCAL_DIR)`

			`ARCH := riscv`
			`SUBARCH ?= 32`
[arch][riscv32] rename the qemu target sifive-e The initial port is really a Sifive E platform. Call it what it is and make space for bringing up the Sifive U and virt qemu target. 2019-02-17 20:20:16 -08:00			`VARIANT ?= sifive_e`
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place. 2018-10-14 17:12:01 -07:00
			`MODULE_DEPS += lib/cbuf`

			`MODULE_SRCS += $(LOCAL_DIR)/platform.c`
			`MODULE_SRCS += $(LOCAL_DIR)/plic.c`
			`MODULE_SRCS += $(LOCAL_DIR)/uart.c`

			`ROMBASE ?= 0x20400000 # if running from rom, start here`
			`MEMBASE ?= 0x80000000`
			`MEMSIZE ?= 0x00100000 # default to 1MB`

[arch][riscv] port to riscv64 Very little needed to port except to conditionalize some assembly in the context switch and exception code. Mostly needed to move build system stuff around and add a new project. 2019-11-02 17:21:13 -07:00			`ifeq ($(VARIANT),sifive_e)`
[platform][riscv-virt] added support for QEMU's riscv 'virt' machine The virt machine is a generic target, much like the arm virt machine. Intended to be simple to use and a good target to run large systems like linux on. At the moment simply support booting and simple uart and timer support. 2019-03-30 21:31:47 -07:00			`# uses a two segment layout, select the appropriate linker script`
			`ARCH_RISCV_TWOSEGMENT := 1`
[arch][riscv] port to riscv64 Very little needed to port except to conditionalize some assembly in the context switch and exception code. Mostly needed to move build system stuff around and add a new project. 2019-11-02 17:21:13 -07:00			`# sets a few options in the riscv arch`
			`ARCH_RISCV_EMBEDDED := 1`
			`endif`
[platform][riscv-virt] added support for QEMU's riscv 'virt' machine The virt machine is a generic target, much like the arm virt machine. Intended to be simple to use and a good target to run large systems like linux on. At the moment simply support booting and simple uart and timer support. 2019-03-30 21:31:47 -07:00
[arch][riscv32] rename the qemu target sifive-e The initial port is really a Sifive E platform. Call it what it is and make space for bringing up the Sifive U and virt qemu target. 2019-02-17 20:20:16 -08:00			`# sifive_e or _u?`
			`GLOBAL_DEFINES += PLATFORM_${VARIANT}=1`

[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place. 2018-10-14 17:12:01 -07:00			`include make/module.mk`