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lk/target/sifive-e/rules.mk

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[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
2018-10-14 17:12:01 -07:00
LOCAL_DIR := $(GET_LOCAL_DIR)
[target][sifive-e] Get LK working on a Sifive Hifive1 board -added support for bringing up the clocks and setting up the gpio bits before starting the uart. -add a proper target init routine -add scripts to flash board via openocd -fixed bug in riscv interrupt save state where it wasn't saving mstatus on irq entry. -comment out cycle enabling, not implemented on this core
2019-02-18 22:05:44 -08:00
MODULE := $(LOCAL_DIR)
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
2018-10-14 17:12:01 -07:00
PLATFORM := sifive
[arch][riscv32] rename the qemu target sifive-e The initial port is really a Sifive E platform. Call it what it is and make space for bringing up the Sifive U and virt qemu target.
2019-02-17 20:20:16 -08:00
VARIANT := sifive_e
[platform][sifive-e] get the hifive1 hardware working again Had rotted a bit. Had to reimplement a few tweaks. Also generally #if out a lot of the SMP code when unused on riscv.
2020-01-18 18:26:52 -08:00
WITH_LINKER_GC ?= 1
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
2018-10-14 17:12:01 -07:00
MEMSIZE ?= 0x4000 # 16KB
[target][sifive-e] Get LK working on a Sifive Hifive1 board -added support for bringing up the clocks and setting up the gpio bits before starting the uart. -add a proper target init routine -add scripts to flash board via openocd -fixed bug in riscv interrupt save state where it wasn't saving mstatus on irq entry. -comment out cycle enabling, not implemented on this core
2019-02-18 22:05:44 -08:00
GLOBAL_DEFINES += TARGET_HAS_DEBUG_LED=1
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
2018-10-14 17:12:01 -07:00
[target][sifive-e] Get LK working on a Sifive Hifive1 board -added support for bringing up the clocks and setting up the gpio bits before starting the uart. -add a proper target init routine -add scripts to flash board via openocd -fixed bug in riscv interrupt save state where it wasn't saving mstatus on irq entry. -comment out cycle enabling, not implemented on this core
2019-02-18 22:05:44 -08:00
# target code will set the master frequency to 16Mhz
GLOBAL_DEFINES += SIFIVE_FREQ=16000000
MODULE_SRCS := $(LOCAL_DIR)/target.c
[arch][riscv] Add basic support for SiFive HiFive Unleashed Most of changes were moving around where macros were defined, plus the following: - Remove requirement for floating point on RV64 to support booting monitor core on U54 SoC. - Add support for Debug LEDs on HiFive Unleashed Board
2019-12-03 15:48:18 -08:00
# set some global defines based on capability
[console] move the history buffer into static memory, remove console_init No need to malloc this memory if it's always going to be initialized anyway. Add history disabling switch to a few targets to make sure both builds are tested.
2020-05-17 16:12:47 -07:00
GLOBAL_DEFINES += CONSOLE_ENABLE_HISTORY=0
[arch][riscv] Add basic support for SiFive HiFive Unleashed Most of changes were moving around where macros were defined, plus the following: - Remove requirement for floating point on RV64 to support booting monitor core on U54 SoC. - Add support for Debug LEDs on HiFive Unleashed Board
2019-12-03 15:48:18 -08:00
GLOBAL_DEFINES += PLATFORM_HAS_DYNAMIC_TIMER=1
GLOBAL_DEFINES += ARCH_RISCV_CLINT_BASE=0x02000000
GLOBAL_DEFINES += ARCH_RISCV_MTIME_RATE=32768
[target][sifive-e] Get LK working on a Sifive Hifive1 board -added support for bringing up the clocks and setting up the gpio bits before starting the uart. -add a proper target init routine -add scripts to flash board via openocd -fixed bug in riscv interrupt save state where it wasn't saving mstatus on irq entry. -comment out cycle enabling, not implemented on this core
2019-02-18 22:05:44 -08:00
include make/module.mk
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
2018-10-14 17:12:01 -07:00
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