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lk/arch/riscv/start.S

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[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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/*
* Copyright (c) 2015 Travis Geiselbrecht
*
[license] replace the longer full MIT license with a shorter one Used scripts/replacelic. Everything seems to build fine.
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* Use of this source code is governed by a MIT-style
* license that can be found in the LICENSE file or at
* https://opensource.org/licenses/MIT
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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*/
[include][lk] fixup lk/ include path move
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#include <lk/asm.h>
[arch][riscv] Expose RISC-V mp kernel start Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation
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#include <arch/defines.h>
#include "config.h"
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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.section ".text.boot"
FUNCTION(_start)
[arch][riscv] set up the global pointer register The linker will automatically relax any dereferences and calculations for symbols located near the symbol __global_pointer$.
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.option push
.option norelax
[platform][riscv] add code to read the size of memory from the FDT Tweak the novm allocator to let us more easily add a variable sized arena at boot. Also added code to trap secondary cpus and reenable the use of WFI instruction.
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// set the global pointer
[arch][riscv] set up the global pointer register The linker will automatically relax any dereferences and calculations for symbols located near the symbol __global_pointer$.
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la gp, __global_pointer$
.option pop
[platform][riscv] add code to read the size of memory from the FDT Tweak the novm allocator to let us more easily add a variable sized arena at boot. Also added code to trap secondary cpus and reenable the use of WFI instruction.
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// if our hart isnt 0, trap the cpu
csrr t0, mhartid
// set the default stack
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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la sp, default_stack_top
[arch][riscv] Expose RISC-V mp kernel start Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation
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// default stack locations for each hart:
// LOW ------------ HIGH
// [hart2][hart1][hart0]
li t1, ARCH_DEFAULT_STACK_SIZE
mul t1, t1, a0
sub sp, sp, t1
// everyone stores zero in _boot_status
la t5, _boot_status
sw zero, (t5)
bnez t0, .Lsecondary_trap
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
2018-10-14 17:12:01 -07:00
[arch][riscv] port to riscv64 Very little needed to port except to conditionalize some assembly in the context switch and exception code. Mostly needed to move build system stuff around and add a new project.
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#if ARCH_RISCV_TWOSEGMENT
[platform][riscv] add code to read the size of memory from the FDT Tweak the novm allocator to let us more easily add a variable sized arena at boot. Also added code to trap secondary cpus and reenable the use of WFI instruction.
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// copy preinitialized data from flash to memory
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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la t0, __data_start_rom
la t1, __data_start
la t2, __data_end
beq t0, t1, 1f
0:
lw t3, (t0)
sw t3, (t1)
add t0, t0, 4
add t1, t1, 4
bne t1, t2, 0b
#endif
[platform][riscv] add code to read the size of memory from the FDT Tweak the novm allocator to let us more easily add a variable sized arena at boot. Also added code to trap secondary cpus and reenable the use of WFI instruction.
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// zero bss
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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1:
la t0, __bss_start
la t1, __bss_end
0:
sw x0, (t0)
add t0, t0, 4
bne t0, t1, 0b
[arch][riscv] Expose RISC-V mp kernel start Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation
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// Release any other harts into riscv_secondary_entry
fence w, w
add t0, zero, 1
sw t0, (t5)
[platform][riscv] add code to read the size of memory from the FDT Tweak the novm allocator to let us more easily add a variable sized arena at boot. Also added code to trap secondary cpus and reenable the use of WFI instruction.
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// call main
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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jal lk_main
[platform][riscv] add code to read the size of memory from the FDT Tweak the novm allocator to let us more easily add a variable sized arena at boot. Also added code to trap secondary cpus and reenable the use of WFI instruction.
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// should never return here
j .
.Lsecondary_trap:
[arch][riscv] Expose RISC-V mp kernel start Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation
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#if WITH_SMP
// wait for _boot_status to be nonzero, then go into riscv_secondary_entry
lw t0, (t5)
beqz t0, .Lsecondary_trap
jal riscv_secondary_entry
#else
[platform][riscv] add code to read the size of memory from the FDT Tweak the novm allocator to let us more easily add a variable sized arena at boot. Also added code to trap secondary cpus and reenable the use of WFI instruction.
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wfi
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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j .
[arch][riscv] Expose RISC-V mp kernel start Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation
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#endif
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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.bss
.align 4
LOCAL_DATA(default_stack)
[arch][riscv] Expose RISC-V mp kernel start Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation
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.skip ARCH_DEFAULT_STACK_SIZE * SMP_MAX_CPUS
[arch][riscv] Initial port to a riscv32 sifive target Currently targets qemu's sifive_e machine, which is a split flash/ram machine, much like the Sifive HiFive1. Untested as of yet on a real HiFive1. Basic support including interrupts and architectural timers in place.
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LOCAL_DATA(default_stack_top)
[arch][riscv] Expose RISC-V mp kernel start Support mp lk start on RISC-V. Several changes throughout were required: - Add signal in asm start to force secondary harts to wait for bss to be cleared. - Use mhartid in arch_curr_cpu_num, PLIC, and CLINT - Use tp register as thread pointer instead of global variable. - Support sending IPIs between harts using CLINT - Add spinlock implementation
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LOCAL_DATA(_boot_status)
.dword
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