lk/target/stm32746g-eval2/rules.mk

LOCAL_DIR := $(GET_LOCAL_DIR)

MODULE := $(LOCAL_DIR)

STM32_CHIP := stm32f746

PLATFORM := stm32f7xx

SDRAM_SIZE := 0x02000000
SDRAM_BASE := 0xc0000000
EXT_SRAM_BASE := 0x68000000
EXT_SRAM_SIZE := 0x00200000

GLOBAL_DEFINES += \
    ENABLE_UART1=1 \
    ENABLE_SDRAM=1 \
    SDRAM_BASE=$(SDRAM_BASE) \
    SDRAM_SIZE=$(SDRAM_SIZE) \
    EXT_SRAM_BASE=$(EXT_SRAM_BASE) \
    EXT_SRAM_SIZE=$(EXT_SRAM_SIZE) \
    ENABLE_EXT_SRAM=1 \
\
    PKTBUF_POOL_SIZE=16

# XXX todo, drive pll config from here
#HSE_VALUE=8000000 \
    PLL_M_VALUE=8 \
    PLL_N_VALUE=336 \
    PLL_P_VALUE=2

MODULE_SRCS += \
    $(LOCAL_DIR)/init.c \
    $(LOCAL_DIR)/lcd.c \
    $(LOCAL_DIR)/sram.c

MODULE_DEPS += \
    lib/gfx \

#    lib/gfxconsole

include make/module.mk
WIP support for stm32f746g-eval2 board 2015-07-08 02:23:55 -07:00			`LOCAL_DIR := $(GET_LOCAL_DIR)`

			`MODULE := $(LOCAL_DIR)`

			`STM32_CHIP := stm32f746`

			`PLATFORM := stm32f7xx`

[target][stm32746g-eval2] add sdram initialization sequence 2015-08-17 11:46:09 -07:00			`SDRAM_SIZE := 0x02000000`
set heap after the lcd memory So that the gfx console commands don't crash LK. 2015-08-18 14:36:32 -07:00			`SDRAM_BASE := 0xc0000000`
[target][stm32746g-eval2] enable external SRAM block, update MPU cache params For future reference: TEX 001 C 1 B 1 S 0 is the full cache params for cortex-m7. 2015-08-19 17:23:11 -07:00			`EXT_SRAM_BASE := 0x68000000`
			`EXT_SRAM_SIZE := 0x00200000`

WIP support for stm32f746g-eval2 board 2015-07-08 02:23:55 -07:00			`GLOBAL_DEFINES += \`
[target][stm32746g-eval2] add sdram initialization sequence 2015-08-17 11:46:09 -07:00			`ENABLE_UART1=1 \`
			`ENABLE_SDRAM=1 \`
			`SDRAM_BASE=$(SDRAM_BASE) \`
			`SDRAM_SIZE=$(SDRAM_SIZE) \`
[target][stm32746g-eval2] enable external SRAM block, update MPU cache params For future reference: TEX 001 C 1 B 1 S 0 is the full cache params for cortex-m7. 2015-08-19 17:23:11 -07:00			`EXT_SRAM_BASE=$(EXT_SRAM_BASE) \`
			`EXT_SRAM_SIZE=$(EXT_SRAM_SIZE) \`
[platform][stm32f7xx] move mpu initialization into platform, set up inaccessible region at 0 2015-09-17 14:06:14 -07:00			`ENABLE_EXT_SRAM=1 \`
[platform][stm32f7xx] wire ethernet driver up to minip Enable it by default on the stm32746g-eval2 platform 2015-08-26 17:55:36 -07:00			`\`
[minip][pktbuf] Move pktbuf allocation to a common pool Rather than having a pool for pktbuf buffers and a pool for pktbufs, move them to a common pool. 2015-09-09 13:41:51 -07:00			`PKTBUF_POOL_SIZE=16`
[target][stm32746g-eval2] add sdram initialization sequence 2015-08-17 11:46:09 -07:00
			`# XXX todo, drive pll config from here`
			`#HSE_VALUE=8000000 \`
			`PLL_M_VALUE=8 \`
			`PLL_N_VALUE=336 \`
			`PLL_P_VALUE=2`
WIP support for stm32f746g-eval2 board 2015-07-08 02:23:55 -07:00
			`MODULE_SRCS += \`
[target][stm32746g-eval2] add sdram initialization sequence 2015-08-17 11:46:09 -07:00			`$(LOCAL_DIR)/init.c \`
[target][stm32746g-eval2] add lcd initialization sequence 2015-08-17 12:33:03 -07:00			`$(LOCAL_DIR)/lcd.c \`
[target][stm32746g-eval2] enable external SRAM block, update MPU cache params For future reference: TEX 001 C 1 B 1 S 0 is the full cache params for cortex-m7. 2015-08-19 17:23:11 -07:00			`$(LOCAL_DIR)/sram.c`
WIP support for stm32f746g-eval2 board 2015-07-08 02:23:55 -07:00
[target][stm32746g-eval2] add support for lk's display/gfx api 2015-08-17 13:36:23 -07:00			`MODULE_DEPS += \`
[target][stm32746g-eval2] add MPU cache region for sdram, clear lcd on boot 2015-08-17 16:00:59 -07:00			`lib/gfx \`

			`# lib/gfxconsole`
[target][stm32746g-eval2] add support for lk's display/gfx api 2015-08-17 13:36:23 -07:00
WIP support for stm32f746g-eval2 board 2015-07-08 02:23:55 -07:00			`include make/module.mk`